Itsuaki Matsuda

Electroless Diffusion Barrier Process Using SAM on Low-k Dielectrics

A wet process based on electroless deposition is proposed for the formation of a diffusion barrier layer for Cu wiring in ultra-large scale integration (ULSI) technology. The diffusion barrier layer is formed on a low-dielectric constant (low-k) inter level film. In this process, a Pd-activated self-assembled monolayer as a seed/adhesion layer was used as a key step to allow electroless deposition on a dielectric film. The effectiveness of this approach was demonstrated by depositing an electroless NiB layer as the diffusion barrier layer. The electrolessly deposited NiB layer showed a uniform surface, a small grain size, and a high adhesion when deposited on various common inter level dielectric materials with low dielectric constant. The electrolessly deposited NiB layer formed on the low-k dielectric film by this method showed a high thermal stability of the effectiveness as a barrier to Cu diffusion at temperatures up to 400°C for 30 min. The electroless process was found to be reproducible and did not affect dielectric properties of the underlying insulator.

Fabrication of Electroless CoWP/NiB Diffusion Barrier Layer on SiO2 for ULSI Devices

We investigated the electroless CoWP/NiB diffusion barrier layer for ultralarge-scale integration (ULSI) interconnection by forming the immobilizing Pd catalyst on an organosilane layer. When the electroless CoWP film was formed directly on a Pd-activated organosilane layer, it became islandlike and did not form a continuous layer. When it was formed on an electroless NiB deposited on a Pd-activated organosilane layer, the electroless CoWP film was uniform and formed a continuous layer 10 nm thick. The transmission electron microscopy images of the interfaces of Cu/CoWP/NiB/SiO 2 showed that, at an annealing temperature up to 400°C for 30 min, the interfaces remained unchanged and clear, showing no trace of Cu diffusion into the SiO 2 substrate. In-plane X-ray diffraction patterns indicated that the CoWP/NiB film had an amorphous structure and was stable against heat-treatment up to 500°C for 30 min. An evaluation of sheet resistance measurements suggested that the CoWP/NiB film shows appropriate barrier properties for Cu diffusion up to 400°C. The CoWP/NiB film was used as a seed for electroless Cu plating. Trenches 100 nm wide were coated with a 10 nm CoWP/NiB barrier followed by successful trench filling by electroless Cu plating.

Effect of organosilane underlayers on the effectiveness of NiB barrier layers in ULSI metallization

A process was developed for producing a barrier layer of NiB by means of electroless deposition on an underlayer of Pd-activated organosilane monolayer formed on the insulator. An attempt was made to decrease the thickness of the NiB layer without adversely affecting its barrier property to make it compatible with further miniaturized ultralarge-scale integration (ULSI) devices of the future. This aim was achieved by using 3-[2-(2-aminoethylamino)ethylamino]propyltrimethoxysilane (TAS) as the underlayer between the NiB layer and the substrate. By using TAS instead of 3-aminopropyltriethoxysilane (APTES) which was used in our previous study, the minimum acceptable thickness of the NiB barrier layer was successfully reduced to 6 nm. The copper deposit formed on the barrier layer in trenches was free of defects, and it was stable even after annealing at 400°C for 30 min.