Iulian Ober

Timed Extensions for SDL

In this paper we propose some extensions necessary to enable the specification and description language SDL to become a more appropriate formalism for the design of real-time and embedded systems. The extensions we envisage concern both roles of SDL: first, in order to make SDL a better real-time specification language, allowing to correctly simulate and verify real-time specifications, we propose a set of annotations to express in a flexible way assumptions and assertions on timing issues such as execution durations, communication delays, or periodicity of external inputs; second, in order to make SDL a better real-time design language, several useful real-time programming concepts are added. In particular we propose to extend the basic SDL timer mechanism by introducing new primitives such as cyclic timers, interruptive timers, and access to timer value. All these extensions rely on a clear and powerful time semantics for SDL, which extends the current one, and which is based on timed automata with urgencies.

Verification of Quantitative Temporal Properties of SDL Specifications

We describe an approach for the verification of quantitative temporal properties of SDL specifications, which adapts techniques developed for timed automata [2]. With respect to other verification approaches applied to SDL, our approach broadens the class of analyzable specifications and improves the handling of non-deterministic systems, such as open systems communicating with an unspecified environment. Compared to the initial framework of timed automata, the application of these verification techniques to SDL raises two interesting issues, discussed in the paper. They are: expressing the semantics of time in SDL in terms of timed automata concepts, and employing a user friendly automata-based property specification language (GOAL [1]) to express and verify temporal properties. The paper also presents a verification tool prototype for SDL which implements these ideas.