Ivan Aleksi

Single-Commodity Vehicle Routing Problem with Pickup and Delivery Service

We present a novel variation of the vehicle routing problem (VRP). Single commodity cargo with pickup and delivery service is considered. Customers are labeled as either cargo sink or cargo source, depending on their pickup or delivery demand. This problem is called a single commodity vehicle routing problem with pickup and delivery service (1-VRPPD). 1-VRPPD deals with multiple vehicles and is the same as the single-commodity traveling salesman problem (1-PDTSP) when the number of vehicles is equal to 1. Since 1-VRPPD specializes VRP, it is 𝒩𝒫 hard in the strong sense. Iterative modified simulated annealing (IMSA) is presented along with greedy random-based initial solution algorithm. IMSA provides a good approximation to the global optimum in a large search space. Experiment is done for the instances with different number of customers and their demands. With respect to average values of IMSA execution times, proposed method is appropriate for practical applications.

Ceramic tiles failure detection based on FPGA image processing

This paper presents one method about automation of tile surface and texture diagnosis. Final stage of tile manufacturing deals with surface and edge defects detection, and is still not an automated part of production. We used computer visual diagnosis and FPGA-based embedded hardware digital design to classify tiles according to surface and edge defects. In order to reduce computing time, we used tile images from line camera and the FPGA embedded parallel image processing unit designed with VHDL.

Step sequence planning for a biped robot by means of a cylindrical shape model and a high-resolution 2.5D map

A novel step sequence planning (SSP) method for biped-walking robots is presented. The method adopts a free space representation custom-designed for efficient biped robot motion planning. The method rests upon the approximation of the robot shape by a set of 3D cylindrical solids. This feature allows efficient determination of feasible paths in a 2.5D map, comprising stepping over obstacles and stair climbing. A SSP algorithm based on A^*-search is proposed which uses the advantages of the aforementioned environment representation. The efficiency of the proposed approach is evaluated by a series of simulations performed for eight walking scenarios.

CPU, GPU and FPGA Implementations of MALD: Ceramic Tile Surface Defects Detection Algorithm

This paper addresses adjustments, implementation and performance comparison of the Moving Average with Local Difference (MALD) method for ceramic tile surface defects detection. Ceramic tile production process is completely autonomous, except the final stage where human eye is required for defects detection. Recent computational platform development and advances in machine vision provides us with several options for MALD algorithm implementation. In order to exploit the shortest execution time for ceramic tile production process, the MALD method is implemented on three different platforms: CPU, GPU and FPGA, and it is implemented on each platform in at least two ways. Implementations are done in MATLABs MEX/C++, C++, CUDA/C++, VHDL and Assembly programming languages. Execution times are measured and compared for different algorithms and their implementations on different computational platforms.

Adaptive Virtual Devices Platform for verification of FPGA modules in student courses on Digital Design

This paper describes the FPGA based verification platform that is dedicated to improve student efficiency for the course on Digital Design with FPGAs. We developed a functional verification platform that extends the number of I/O devices, which is usually limited on development kits. Simple PicoBlaze CPU-based design is used to synchronize the input and output signals between PC and the FPGA. Complete verification platform occupies only 14% of the Spartan 3 XC3S200 FPGA device. During the course, students get the knowledge about the PicoBlaze CPU and its assembly language, as well as getting familiar with the FPGAs and VHDL. At the end of the lectures, students are able to understand the HW/SW co-design and to use the verification platform for making their final project.

Real-time Biscuit Tile Image Segmentation Method Based on Edge Detection

In this paper we propose a novel real-time Biscuit Tile Segmentation (BTS) method for images from ceramic tile production line. BTS method is based on signal change detection and contour tracing with a main goal of separating tile pixels from background in images captured on the production line. Usually, human operators are visually inspecting and classifying produced ceramic tiles. Computer vision and image processing techniques can automate visual inspection process if they fulfill real-time requirements. Important step in this process is a real-time tile pixels segmentation. BTS method is implemented for parallel execution on a GPU device to satisfy the real-time constraints of tile production line. BTS method outperforms 2D threshold-based methods, 1D edge detection methods and contour-based methods. Proposed BTS method is in use in the biscuit tile production line.

Digital chess board based on array of Hall-Effect sensors

This paper addresses a novel concept of digital chess board realized with an array of Hall-Effect sensors. Main task of digital chess board is autonomous detection of players moves. Therefore, players do not have to write down their own moves on a sheet of paper. Non-invasive piece moves detection is considered, with minimum required installations in a game room. The digital chees board presented in this paper has a Hall-Effect sensor placed under the middle of each field on the chess board, while each chess piece has a permanent magnet placed on its bottom. Sensors, total of 64, are organized as 8×8 array. Microcontroller reads sensor data and sends them to a remote PC for storage in a database and board visualization. Rows are multiplexed in time, i.e. one row is active in a certain time instance. States in the column of the currently active row are stored in a corresponding matrix column. Con to this approach is in its ability to detect piece presence on the field, without the information about the piece type. The proposed approach is low cost, non-invasive and requires only power and communication cable.

Simulation environment for creating artificial range data in underwater object reconstruction

This paper proposes a simulation environment for creating simulated ranging data of high resolution sonar systems. It enables the assessment of underwater object reconstruction techniques and the verification of various methods for automated target detection. As an input, the proposed environment uses the AUVs trajectory, a model of the sonar system attached to the AUV and 3D CAD models of underwater objects. As an output one can get a point cloud of the whole underwater object or 2D images, i.e. range data, which are smaller parts of a large objects 3D model. Noise is modeled and used as additional input in order to generate outputs that are closer to the real-world. The simulated data is processed and evaluated, where well known sonar signal processing methods are used to process the simulated acoustic signals. Automated target detection is achieved by processing the simulated 2D range data with advanced image processing techniques.

FPGA Verification Module

This paper addresses verification and debugging tool for development of FPGA modules. Proposed tool is developed for educational purposes in teaching students on Digital Design and VHDL programming language. Main goal of the debugging module is to get/set signal values while the FPGA board is running the module of interest. Two PicoBlaze CPUs are used in order to synchronize the input and output signals between PC and the FPGA. Debugging and verification tool is wrapped around the testing module, and it occupies 14% of the Spartan 3 XC3S200 FPGA device. While using proposed tool, students are getting the knowledge about the PicoBlaze CPU, assembly language, FPGA, VHDL. When using proposed tool, students get deeper understanding of the hardware-software co- design concept. Finally, individual tasks are assigned to student workgroups. Some typical tasks are illustrated in this paper.