Ivan S. Esqueda

Two-dimensional methodology for modeling radiation-induced off-state leakage in CMOS technologies

A modeling approach using two-dimensional device simulations is presented, which enables the extraction of parameters for the radiation-induced parasitic MOSFET created at the edge of the shallow trench isolation (STI) oxide. With the model, one can estimate drain-to-source off-state leakage current (I/sub OFF/) resulting from build-up of oxide trapped charge (N/sub OT/). The impact of nonuniform N/sub OT/ build-up in the STI resulting from total ionizing dose (TID) exposure and external bias conditions is analyzed through volumetric simulations and compared to experimental data. Saturation for the off-state leakage current as a function of trapped charge is also investigated.

Modeling ionizing radiation effects in solid state materials and CMOS devices

A comprehensive model is presented which enables the effects of ionizing radiation on bulk CMOS devices and parasitic structures to be simulated with closed form functions. The model adapts general equations for defect formation in uniform SiO2 films to facilitate analytical calculations of trapped charge and interface trap buildup in radiation sensitive shallow trench isolation (STI) oxides. An approach whereby defect distributions along the bottom and sidewall of the STI are calculated, incorporated into implicit surface potential equations, and ultimately used to model radiation-induced leakage currents in MOSFET structures and integrated circuits is described. The results of the modeling approach are compared to experimental data obtained on 130 and 90 nm devices and circuits. The features having the greatest impact on the increased radiation tolerance of advanced deep-submicron bulk CMOS technologies are also discussed. These features include increased doping levels along the STI sidewall.

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices.

Modeling of Ionizing Radiation-Induced Degradation in Multiple Gate Field Effect Transistors

The radiation response of advanced non-planar multiple gate field effect transistors (MuGFETs) has been shown to have a strong dependence on fin width (W). The incorporation of total ionizing dose (TID) effects into a physics-based surface-potential compact model allows for the effects of radiation-induced degradation in MuGFET devices to be modeled in circuit simulators, e.g., SPICE. A set of extracted parameters are used in conjunction with closed-form expressions for the surface potential, thereby enabling accurate modeling of the radiation-response and its dependence on W . Total ionizing dose (TID) experiments and two-dimensional (2D) TCAD simulations are used to validate the compact modeling approach presented in this paper.

Modeling the Radiation Response of Fully-Depleted SOI n-Channel MOSFETs

A continuous analytical model for radiation-induced degradation in fully-depleted (FD) silicon on insulator (SOI) n-channel MOSFETs is presented. The combined effects of defect buildup in the buried oxide and band-to-band tunneling (BBT) have been shown to be the primary mechanisms that determine the radiation effects on the electrical characteristics. Closed-form expressions for the front and back-gate surface potential incorporate these effects, thereby enabling accurate modeling of the degraded current voltage characteristics that result from ionizing radiation exposure.

Modeling Inter-Device Leakage in 90 nm Bulk CMOS Devices

We demonstrate an analytical modeling approach that captures the effects of total ionizing dose (TID) on the Id -Vgs characteristics of field-oxide-field-effect-transistors (FOXFETs) fabricated in a low-standby power commercial bulk CMOS technology. Radiation-enabled technology computer aided design (TCAD) simulations and experimental data allow validating the model against technological parameters such as doping concentration, field-oxide thickness, and geometry. When used in conjunction with the closed-form expressions for the surface potential, the analytical models for fixed oxide charge and interface trap density enables accurate modeling of radiation-induced degradation of the FOXFET Id -Vgs characteristics allowing the incorporation of TID into surface potential based compact models.

Modeling Low Dose Rate Effects in Shallow Trench Isolation Oxides

Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that there is a dose rate enhancement factor (EF) associated with radiation-induced degradation. One dimensional (1-D) numerical calculations are used to investigate the key mechanisms responsible for the dose rate dependent buildup of radiation-induced defects in shallow trench isolation (STI) oxides. Calculations of damage EF indicate that oxide thickness, distribution of hole traps and hole capture cross-section affect dose rate sensitivity. The dose rate sensitivity of STI oxides is compared with the sensitivity of bipolar base oxides using model calculations.

Modeling the effects of hydrogen on the mechanisms of dose rate sensitivity

The effects of hydrogen on dose-rate sensitivity are simulated using a one-dimensional (1-D) model that incorporates the physical mechanisms contributing to dose-rate effects in metal-oxide-semiconductor (MOS) structures. Calculations show that molecular hydrogen cracking at positively charged defects may be a key reaction relating hydrogen and dose rate response. Comparison to experimental data on bipolar devices results in good agreement with the dose rate calculations of interface trap buildup.

Impact of Low Temperatures

Total ionizing dose characteristics and dose rate dependence are evaluated under low temperature conditions for gated lateral PNP bipolar junction transistors. The results show that the dose rate sensitivity of the examined linear bipolar circuit technology is reduced when irradiations are performed at low temperature. The results are supported by numerical simulations that model low temperature behaviors through the suppression of hole and proton transport in the irradiated oxide. These findings agree well with previous studies of CMOS technologies, which reported on the time and bias dependence of defect buildup in MOS capacitors and transistors. This study of temperature effects on the total dose and dose rate response of PNP BJTs expands upon these works by examining the impact of low temperature on ELDRS in bipolar technologies.

({ on the Total Ionizing Dose Response and ELDRS in Gated Lateral PNP BJTs

It was recently shown that radiation hardened by design (RHBD) annular-gate MOSFETs not only provide totaldose radiation tolerance, but can also improve the hot-carrier reliability of advanced CMOS circuits. In this paper, the hotcarrier reliability of standard two-edge and enclosed geometry transistors intended for use in space and strategic environments is demonstrated. Hot-carrier reliability measurements on standard two-edge, standard enclosed, gate under-lap enclosed, and annular transistors fabricated in the same 90 nm high performance technology indicate an improvement in hot-carrier lifetime in the enclosed geometry and multi-finger transistor designs when compared to a conventional single stripe MOSFET. Two-dimensional device simulations, along with experimental measurements, provide physical insight into the reliability response of each device type.