Ivar Løkken

Quantizer Nonoverload Criteria in Sigma–Delta Modulators

A simple method to guarantee absolute stability in multibit sigma-delta modulators (SDMs) is to ensure that the quantizer never overloads. This applies to any SDM. Derivation of the requirements for nonoverload have previously been shown for different types of modulators; the sigma-delta or output-feedback modulator with rounding quantizer as well as the error-feedback modulator using truncation. Here, these nonoverload requirements will be clarified and a unified formulation is presented that is not limited with regard to modulator topology or quantizer function

High-level continuous-time sigma delta design in Matlab/Simulink

This paper presents a framework for behavioral simulations of continuous time delta-sigma modulators (CTSD) developed in Matlab/Simulink. Error sources in CTSD designs are reviewed and it is explained how sub-module specifications can be derived from a system-level target performance. The paper also discusses considerations of importance when using Simulink for CTSD modelling, like the choice of solver and simulation speed optimization. An example CTSD design is used throughout to illustrate the results and error models.

A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS

A 5th order continuous time delta sigma modulator is designed in 0.18μm CMOS. At a sampling rate of 500MHz it achieves 76dB SNDR over a 10MHz bandwidth consuming 58mW. 5th order noiseshaping is realized with 4 opamp based RC integrators and a VCO realizing an integrator and a 4 bit quantizer. A THD of -82.3dBc is achieved without calibration of feedback DACs. A high speed capacitive implementation of excess loop delay compensation, together with a method for reducing the switching activity of the output codes from the VCO are proposed.