Ivo Bolsens

Analysis and experimental verification of digital substrate noise generation for epi-type substrates

Substrate coupling in mixed-signal ICs can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends.

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on the analog circuits, information is needed about digital substrate noise generation. A methodology for modelling and simulating the time-domain waveform of the generated substrate noise of large digital circuits is verified with measurements on an 86k-gate CMOS ASIC. The difference between simulated and measured substrate noise RMS voltage is <10% and simulation time is of the same order of magnitude as a gate-level VHDL simulation. For smaller circuits, e.g., a 1k-gate multiplier, a speedup in simulation time of 3 orders of magnitude is obtained with respect to a full SPICE simulation.

Impact of front-end non-idealities on bit error rate performance of WLAN-OFDM transceivers

New OFDM-based WLAN standards target wireless communications in the 5 GHz band for consumer multimedia applications. Given the high data rates with required low bit error rates, and given the nature of the OFDM signal, a conservative analysis of the front-end requirements lead to severe, over dimensioned specifications. Such a design would never meet this market, by necessity low-cost and low-power. To extract more optimal front-end specifications, we assess the BER performance of the complete WLAN-OFDM link. As a result, we first show that the transmitted symbols word-length can be restricted to 8-bit and the normalized crest factor digitally limited at baseband to 4. Then we show that the power amplifier can operate with only 5.4 dB back-off between the average input power and the input-referred P/sub ldB/. Finally, we quantify in terms of implementation loss the influence of the I/Q imbalance and of the frequency synthesizer phase noise.

80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band

With the advent of mobile communications, voice telecommunications became wireless. Future applications, however, target multimedia, messaging, and high-speed Internet access, all expressing the need for a broadband high-speed wireless access technique. Both the domestic multimedia and the wireless local area network (WLANs) business markets are addressed. Established systems deliver 2-11 Mb/s based on spectrally inefficient spread-spectrum techniques, where scalability has reached a limit. The next generation of modems requires spectrally more efficient low-power and highly integrated solutions. We describe here the design of two digital baseband orthogonal frequency division multiplex (OFDM) signal processing ASICs, implementing respectively a quaternary phase-shift keying (QPSK)-based 80-Mb/s and a 64 quadrature amplitude modulation (QAM)-based 72-Mb/s digital inner transceiver. The latter partially matches the Hiperlan/2 and IEEE 802.11a standards. Joint development of signal processing algorithms and architectures along with on-chip data transfer, control, and partitioning leads to a low-power, yet flexible and scalable implementation. Both ASICs were designed in a unique object-oriented C++ design flow starting from algorithm level. The ASICs were successfully tested in a 5-GHz testbed both for file data transfer and web-cam multimedia transmission.

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

A design experiment for measurement of the spectral content of substrate noise in mixed-signal integrated circuits

In mixed-signal ASICs coupling from switching digital nodes and from the digital power supply to analog circuits via the common substrate can degrade the performance of the analog circuits. This paper describes a design experiment to measure the time domain behavior and spectral content of such substrate coupling noise. To measure this noise over a wide frequency range a novel analog substrate noise sensor has been designed. Using this sensor, substrate noise has been measured in the time and frequency domain. Also the influence of supply voltage, switching activity and mounting technique on the substrate noise are experimentally investigated. Simulation results, using a SPICE substrate model, are also included. The presented measurements show that careful investigation of the spectral content of substrate noise is important in the design of mixed-signal ASICs. Differences between the peak noise levels and the noise floor can easily be 40 dB.

Design Technology for Networked Reconfigurable FPGA Platforms

Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. The paper demonstrates that FPGAs are a realistic implementation platform for thin server or client applications. FPGAs can offer the same end-user experience as software based systems, combined with more computational power and lower cost.

Fast, cheap and under control: the next implementation fabric

Overview The semiconductor industry is caught on two homs of the economics dilemma: (1) the economics of technology deepsubwavelength lithography and equipment cost, reticle enhancement technology and mask cost, and manufacturing variability and yield; and (2) the economics of design productivity design turnaround time, availability of design skills, and portability of design effort. Standard-cells and the RTL methodology have taken us into the 90nm generation, but design is slow, expensive, and out of control. What we need is a next-generation fabric that will once again provide designers with “fast, cheap, and under control” implementation. The question: which fabric? How deeply must the concept of regularity be engrained in the silicon implementation fabric to enable adequate yield and cost control in the face of CD variation and high mask NRE cost? Via-programmable fabrics such as eASIC (VPGA) provide an intermediate design point in the cost-density-performance space, but is this offering sufficiently attractive (let alone defensible)? Or, will traditional FPGAs continue to take up more of the market, starting from their foothold in low-volume and/or reconfigurable applications? On the other hand, regularity and programmability incur cost and performance losses as they abandon the leading edge of the scaling curve. Are such losses growing, and will we therefore always see viable ASIC and COT businesses? Finally, what are the views and needs of the platform SOC and pure-play foundry constituencies?Overview The semiconductor industry is caught on two horns of the economics dilemma: (1) the economics of technology deepsubwavelength lithography and equipment cost, reticle enhancement technology and mask cost, and manufacturing variability and yield; and (2) the economics of design productivity design turnaround time, availability of design skills, and portability of design effort. Standard-cells and the RTL methodology have taken us into the 90nm generation, but design is slow, expensive, and out of control. What we need is a next-generation fabric that will once again provide designers with “fast, cheap, and under control” implementation. The question: which fabric? How deeply must the concept of regularity be engrained in the silicon implementation fabric to enable adequate yield and cost control in the face of CD variation and high mask NRE cost? Via-programmable fabrics such as eASIC (VPGA) provide an intermediate design point in the cost-density-performance space, but is this offering sufficiently attractive (let alone defensible)? Or, will traditional FPGAs continue to take up more of the market, starting from their foothold in low-volume and/or reconfigurable applications? On the other hand, regularity and programmability incur cost and performance losses as they abandon the leading edge of the scaling curve. Are such losses growing, and will we therefore always see viable ASIC and COT businesses? Finally, what are the views and needs of the platform SOC and pure-play foundry constituencies?

Challenges and Opportunities for FPGA Platforms

Today, FPGA devices contain up to 10 million system gates [1] and within three to four years processing technology will allow us to build 50 million gate devices, i.e. enough logic to build very complex, high performance systems. In addition, these devices operate at internal clock speeds, the equal of most ASICs. Although the opportunities for building complex systems with these FPGA platforms are unprecedented, new breakthroughs will be required to solve

A digital 80 Mb/s OFDM transceiver IC for wireless LAN in the 5 GHz band

Emerging standards for broadband wireless LANs (WLANs) such as IEEE802.11a, Hiperlan-II and MMAC require orthogonal frequency division multiplex (OFDM) modulation for the physical layer (PHY) interface. OFDM modems were previously realized in the context of very high speed digital subscriber lines (VDSL) and digital audio broadcast (DAB). However, the WLAN application puts different constraints on the OFDM transceiver presented here because the terminals are portable. Therefore, an adaptive frequency domain equalizer is integrated to mitigate the variations of the indoor wireless channel. Fast programmable on-chip acquisition hardware supports burst mode communications.