J. Biela

SiC versus Si—Evaluation of Potentials for Performance Improvement of Inverter and DC–DC Converter Systems by SiC Power Semiconductors

Switching devices based on wide bandgap materials such as silicon carbide (SiC) offer a significant performance improvement on the switch level (specific on resistance, etc.) compared with Si devices. Well-known examples are SiC diodes employed, for example, in inverter drives with high switching frequencies. In this paper, the impact on the system-level performance, i.e., efficiency, power density, etc., of industrial inverter drives and of dc-dc converter resulting from the new SiC devices is evaluated based on analytical optimization procedures and prototype systems. There, normally on JFETs by SiCED and normally off JFETs by SemiSouth are considered.

PWM Converter Power Density Barriers

Power density of power electronic converters in different applications has roughly doubled every 10 years since 1970. Behind this trajectory was the continuous advancement of power semiconductor device technology allowing an increase of converter switching frequencies by a factor of 10 every decade. However, todays cooling concepts, and passive components and wire bond interconnection technologies could be major barriers for a continuation of this trend. For identifying and quantifying such technological barriers this paper investigates the volume of the cooling system and of the main passive components for the basic forms of power electronics energy conversion in dependency of the switching frequency and determines switching frequencies minimizing the total volume. The analysis is for 5 kW rated output power, high performance air cooling, advanced power semiconductors, and single systems in all cases. A power density limit of 28 kW/dm3@300 kHz is calculated for an isolated DC-DC converter considering only transformer, output inductor and heat sink volume. For single-phase AC-DC conversion a general limit of 35 kW/dm3 results from the DC link capacitor required for buffering the power fluctuating with twice the mains frequency. For a three-phase unity power factor PWM rectifier the limit is 45 kW/dm3@810 kHz just taking into account EMI filter and cooling system. For the sparse matrix converter the limiting components are the input EMI filter and the common mode output inductor; the power density limit is 71 kW/dm3@50 kHz when not considering the cooling system. The calculated power density limits highlight the major importance of broadening the scope of research in power electronics from traditional areas like converter topologies, and modulation and control concepts to cooling systems, high frequency electromagnetics, interconnection technology, multi-functional integration, packaging and multi-domain modeling and simulation to ensure further advancement of the field along the power density trajectory.

A comparative evaluation of isolated bi-directional DC/DC converters with wide input and output voltage range

The working principles and design equations of four different isolated, bi-directional DC to DC converter topologies (a dual active bridge converter, a series resonant converter and two multiple stage topologies) for a 2 kW bi-directional battery charger that can be operated in a wide input and output voltage range are presented in this paper. The results of a detailed mathematical analysis of the converter topologies as well as digital simulation results are used to select the most efficient topology for this specific converter application, where the two-stage series resonant converter is identified to be the most promising, with up to 90% efficiency at rated power.

Using Transformer Parasitics for Resonant Converters—A Review of the Calculation of the Stray Capacitance of Transformers

Parasitic capacitances of conventional transformers can be used as resonant elements in resonant DC-DC converters in order to reduce the overall system size. For predicting the values of the parasitic capacitors without building the transformer different approaches for calculating these capacitances are compared. A systematic summary of the known approaches is given and missing links between the different theories and missing equations are added. Furthermore, a new simple procedure for modelling parasitic capacitances which is based on the known approaches is proposed. The resulting equations are verified by measurements on four different high voltage transformers.

Impact of Power Density Maximization on Efficiency of DC–DC Converter Systems

The demand for decreasing costs and volume leads to a constantly increasing power density of industrial converter systems. In order to improve the power density further different aspects, like thermal management and electromagnetic effects must be considered in conjunction with the electrical design. Therefore, a comprehensive optimization procedure based on analytical models for minimizing volume of DC-DC converter systems has been developed at the Power Electronic Systems Laboratory of the ETH Zurich. Based on this procedure three converter topologies - a phase shift converter with current doubler and with capacitive output filter and a series-parallel resonant converter - are optimized with respect to power density for a telecom supply (400V/48V). There, the characteristic of the power density, the efficiency and the volume distribution between the components as function of frequency is discussed. For the operating points with maximal power density also the loss distribution is presented. Further more, the sensitivity of the optimum with respect to junction temperature, cooling and core material is investigated. The highest power density is achieved by the series-parallel resonant converter. For a 5 kW supply a density of approximately 12 kW/ltr. and a switching frequency of ca. 130 kHz results.

1 Megawatt, 20 kHz, isolated, bidirectional 12kV to 1.2kV DC-DC converter for renewable energy applications

The design of a 1 MW, 20 kHz, isolated, bidirectional 12kV to 1.2kV DC-DC converter for renewable energy applications is presented. The main topics addressed are: High-Voltage (HV) side switch, topology & modulation and Medium Frequency (MF) transformer. A study of the possible HV side switches, considering 4.5kV IGBTs is performed, fixing the requirements from the topology and modulation side in order to reach a highly efficient system. The studied topologies are the Dual Active Bridge (DAB) with triangular modulation and the Series Resonant Converter (SRC) with constant frequency operation. Both topologies are able to achieve Zero Current Switching (ZCS) in the HV side switches, reducing the switching losses in these devices, which contribute to a large share to the system losses. Efficiency curves are presented for different semiconductor technologies for the Low-Voltage (LV) side switch in order to study the trade-offs between the selected topologies. Three MF transformer concepts, namely core-type, shell-type and matrix transformer, are presented and compared in respect of winding arrangement, isolation mechanisms and thermal management. Power losses and volume are calculated in each case and used to compare the different transformer concepts.

Passive and Active Hybrid Integrated EMI Filters

Two new planar integrated EMI filter structures which reduce the filter volume and which are based on standard PCB process technology are presented in this paper. First, a passive integrated EMI filter is presented, which results in a volume reduction of 25% compared to the discrete solution. However, this filter requires a planar ferrite core for the CM inductor. In order to eliminate the ferrite core and reduce the filter volume further (-40% vs. discrete filter) a passive integrated structure is combined with an active EMI filtering circuit. The transfer function, the volume and the losses of the discrete and the two integrated filters, which are designed for a 600W PFC converter, are compared.

Exploring the pareto front of multi-objective single-phase PFC rectifier design optimization - 99.2% efficiency vs. 7kW/din 3 power density

Up to now, in the development of power electronics systems, the reduction of the initial costs or the increase of the power density have been of primary concern. However, with increasing energy costs also the power conversion efficiency is gaining higher and higher importance. Accordingly, while maintaining high power density, an efficiency as high as possible must be obtained. In this paper the maximum attainable efficiency and the dependency of the efficiency limit on technological parameters is determined for single-phase PFC boost rectifiers. In a first step basic PFC boost rectifier topologies are briefly compared with regard to high efficiency and a dual-boost PFC rectifier with integral common-mode filtering is selected as basis for the investigations. Next, simple approximations of the technological limits of the system performance are calculated in the efficiencypower density plane. With this, the Feasible Performance Space and the reduction in power density which has to be accepted for increasing the efficiency are clarified, and the trade-off limit curve (Pareto Front) of a multi-objective, i.e. efficiency and power density design optimization is determined. Furthermore, a comprehensive numerical efficiency optimization is carried out which identifies an efficiency limit of 99.2% for a 3.2kW system. The theoretical considerations are verified by experimental results from a laboratory prototype of the ultra-high efficiency system achieving 99.1% efficiency at a power density of 1.1kW/din3, as well as those firom an ultra-compact dual-boost PFC rectifier (95.8%, 5.5kW/dn3) and a very low switching freluency (3kHz) conventional PFC boost rectifier (96.7%, 2kW/din3). Finally, the sensitivity of the efficiency optimum with regard to various technological parameters is analyzed and an outlook on the further course of the research is given.

Design of a 5-kW, 1-U, 10-kW/dm

The demand for decreasing cost and volume and also for increasing efficiency leads to a constantly increasing power density of converter systems. For maximizing the power density of a 5 kW telecom supply, an optimization procedure that automatically balances the switching frequency, semiconductor and passive losses, and thermal performance has been developed. This procedure and the belonging analytical converter and transformer models are presented in this paper. Moreover, the resulting optimized design, which has a power density of 10 kW/dm 3 and an efficiency of 94.5% at a height of 1 U, is presented.

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The design of a single-phase boost power-factor-correction (PFC) circuit is associated with a large variety of considerations, such as the following questions. Which operation mode should be selected (e.g., continuous or discontinuous operation)? How many interleaved boost cells are advantageous? Which switching frequency should be selected? What is the optimum number of EMI input filter stages? Which semiconductor technology should be chosen? All these issues have a significant influence on the converter efficiency and power density. In this paper, the aforementioned questions are addressed for exemplary specifications of the PFC (300-W output power, 400-V output voltage, and 230-V mains voltage), whereby the focus in the design is mainly put on very high power density. As a result, different design points are identified and comparatively evaluated. By considering different aspects such as volume, losses, capacitor lifetime, and also cost issues (e.g., by additional current sensors or expensive silicon carbide devices), a dual-interleaved PFC operated in discontinuous conduction mode at 200 kHz is selected. With an experimental prototype, a superior power density of 5.5 kW/L and a system efficiency of 96.4% are achieved, which is close to the values predicted by the design procedure. Furthermore, measurements verify a near-unity power factor (PF = 99.7%) and the compliance with electromagnetic compatibility conducted noise emission standards. Finally, it is investigated to which extent the power density could be further increased by an integration of the input filter in the PCB.