J. Bormans

Algorithmic and architectural co-design of a motion-estimation engine for low-power video devices

Due to the large amount of data transfers it involves, the motion estimation (ME) engine is one of the most power-consuming components of any predictive video codec. As a consequence, power-optimized video coding primarily relies on a carefully designed motion estimator. This paper first presents a block ME algorithm that meets high-quality inter-frame prediction and low computational complexity requirements. It relies on a set of rules common to all recent fast and adaptive ME algorithms, but is designed in order to allow for easy and prolific data reuse. The adjacent order of the candidate positions during the search increases the locality and maintains a near-regular data flow, which results in a decrease of the data transfers and a low control complexity. Together with the computational complexity reduction, it enables cost-efficient very large scale integration realizations. A pipelined parallel architecture is then proposed and discussed. It is generic in the sense that it is suited both to the full-pel and half-pel ME. It is efficient because it allows for close to 100% hardware utilization and a sharp decrease of the peak memory bandwidth. It is suited to low-power implementation, as it enables larger data reuse factors for the most probable stages of the adaptive algorithm, which reduces the average memory bandwidth and power consumption.

3D computational graceful degradation

With new multimedia standards, such as MPEG-4, media can progressively be transmitted at different levels of detail, which allows dynamic adaptation to the available network bandwidth. We present a new technique, 3D Computational Graceful Degradation (CGD), that exploits this incremental coding/decoding process to constrain the terminals processing requirements to a predefined level, independently of the degree of complexity of the incoming data. Our attention is directed at 3D scenes, for which the variability of content complexity can range over several orders of magnitude. We provide evidence that the load of the 3D decoding and rendering modules can predictively be estimated and controlled, using a limited amount of statistical measures of the incoming 3D data.

Memory centric design of an MPEG-4 video encoder

The cost-efficient implementation of video codecs requires a set of methodologies and decision taking at different levels in the design flow. We combine upfront algorithmic tuning with memory centric optimizations to transform the video application into a system consisting of functional blocks with localized data processing and a tailored memory hierarchy. This memory optimized functional description is the leverage for the cost-efficient mapping of the system on integrated multimedia platforms. It closely reflects the real implementation constraints and consequently allows for steering the architecture selection in a correct way. The proposed approach is demonstrated on a MPEG-4 video encoder and leads to its implementation as a pipelined system. Hardware development of the motion estimation validates that the high-level memory centric concepts are applicable and realizable at the lowest level. The motion estimation kernel supports up to 30 CIF f/s with minimized processing element requirements and data input rates.

A fractal-based region-oriented color image compression scheme for VLSI implementation

We propose a method for compressing color images using region-oriented coding techniques. After formulating both the image processing and the VLSI implementation demands, we compare different region-oriented approaches, thereby demonstrating the superiority of the Hilbert fractal-based approach.

Terminal QoS for real-time 3-D visualization using scalable MPEG-4 coding

Terminal quality of service is the process of optimally scaling down the decoding and rendering computations to the available processing power, while maximizing the overall perceived quality. This process is applied in a real-time three-dimensional (3-D) decoding and rendering engine, exploiting scalable MPEG-4 coding algorithms. We derive a relation between the quality of the 3-D rendered objects and their processing requirements, expressed by simple CPU time models. The performance dependency parameters are in direct relation to the high-level 3-D content characteristics (number of triangles, number of rendered screen pixels per object) and are calibrated for the platform under test. Examples show that, for any pre-established frame rate, the platform workload can reliably be anticipated for adjusting the content and process parameters accordingly.

Hierarchical fractal-based segmentation of color images

A color image segmentation scheme for use in demanding applications is presented. A complexity reduction is performed by transforming the 3D RGB color space into a 1D length space. The constraints that are put on this transform will be enumerated, and a specific Hilbert fractal-based transform will be selected. The segmentation scheme has been designed to preserve the intrinsic multiresolution clustering properties, allowing for a fast and consistent iteration towards a given range of regions or contour pixels. VLSI implementation will be discussed.

Efficient computation of the two-dimensional fast cosine transform

An extension of one of the fastest existing algorithms for the computation of the 2D discrete cosine transform is given. The algorithm can be implemented in-place requiring N2 less memory locations and 2N2 less data transfers for the computation of NXN DCT points compared to existing 2D FCT algorithms. Based on the proposed algorithm, a fast pruning algorithm is derived for computing the N0xN0 lowest frequency components of a length NXN discrete cosine transform, with both N and N0 being powers of 2. The computational complexity of the algorithm is compared with the row-column pruning method and experimental results on execution times are given.