J. Christiansen

An integrated 16-channel CMOS time to digital converter

An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1 /spl mu/m CMOS technology. The resolution is 156ns and the total time history is 204.8 ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm/sup 2/. The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers. >

A flexible multi-channel high-resolution time-to-digital converter ASIC

A data driven multi-channel time-to-digital converter (TDC) circuit with programmable resolution (/spl sim/25 ps-800 ps binning) and a dynamic range of 102.4 /spl mu/s has been implemented in a 0.25 /spl mu/m CMOS technology. An on-chip PLL is used for clock multiplication up to 320 MHz from an external 40 MHz reference. A 32 element delay locked loop (DLL) performs time interpolation down to 97.5 ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5 ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation.

An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 /spl mu/m CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size 0.15 ns. Used as a TDC device a RMS error of 76 ps has been obtained. A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives. >

Receiver ASIC for timing, trigger and control distribution in LHC experiments

An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and make them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognising individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a PINFET preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1 /spl mu/m CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow to phase shift the system clock and the first level trigger accept signal up to a maximum of sixteen clock cycles in steps of 0.1 ns.

Beam test results for new full-scale GEM prototypes for a future upgrade of the CMS high-η Muon System

The CMS GEM collaboration is considering Gas Electron Multipliers (GEMs) for upgrading the CMS forward muon system in the 1.5 <; |η| <; 2.4 endcap region. GEM detectors can provide precision tracking and fast trigger information. They would improve the CMS muon trigger and muon momentum resolution and provide missing redundancy in the high-η region. Employing a new faster construction and assembly technique, we built four full-scale Triple-GEM muon detectors for the inner ring of the first muon endcap station. We plan to install these or further improved versions in CMS during the first long LHC shutdown in 2013/14 for continued testing. These detectors are designed for the stringent rate and resolution requirements in the increasingly hostile environments expected at CMS after the second long LHC shutdown in 2018/19. The new prototypes were studied in muon/pion beams at the CERN SPS. We discuss our experience with constructing the new full-scale production prototypes and present preliminary performance results from the beam test. We also tested smaller Triple-GEM prototypes with zigzag readout strips with 2 mm pitch in these beams and measured a spatial resolution of 73 μm. This readout offers a potential reduction of channel count and consequently electronics cost for this system while maintaining high spatial resolution.

Construction and performance of large-area triple-GEM prototypes for future upgrades of the CMS forward muon system

At present, part of the forward RPC muon system of the CMS detector at the CERN LHC remains uninstrumented in the high-η region. An international collaboration is investigating the possibility of covering the 1.6 &#60; |η| &#60; 2.4 region of the muon endcaps with large-area triple-GEM detectors. Given their good spatial resolution, high rate capability, and radiation hardness, these micro-pattern gas detectors are an appealing option for simultaneously enhancing muon tracking and triggering capabilities in a future upgrade of the CMS detector. A general overview of this feasibility study will be presented. The design and construction of small (10×10 cm2) and full-size trapezoidal (1 × 0.5 m2) triple-GEM prototypes will be described. During detector assembly, different techniques for stretching the GEM foils were tested. Results from measurements with x-rays and from test beam campaigns at the CERN SPS will be shown for the small and large prototypes. Preliminary simulation studies on the expected muon reconstruction and trigger performances of this proposed upgraded muon system will be reported.

An asynchronous data-driven event-building scheme based on ATM switching fabrics

Asynchronous transfer mode (ATM) packet-switching network technology is proposed as the interconnect for building high-performance, scalable data acquisition architectures. This paper introduces the relevant characteristics of ATM and describes components for the construction of an ATM-based event builder: (1) a multi-path, self-routing, scalable ATM switching fabric, (2) an experimental high performance workstation ATM-interface, and (3) a VMEbus ATM-interface. The requirement for traffic shaping in ATM-based event-builders is discussed and an analysis of the performance of several such schemes is presented. >

Status of the Triple-GEM project for the upgrade of the CMS Muon System

The CMS GEM collaboration is performing a feasibility study to install triple-GEM detectors in the forward region of the muon system (1.6 < vertical bar eta vertical bar < 2.4) of the CMS detector at the LHC. Such micro-pattern gas detectors are able to cope with the extreme particle rates that are expected in that region during the High Luminosity phase of the LHC. With their spatial resolution of order 100 micron GEMs would not only provide additional benefits in the CMS muon High Level Trigger, but also in the muon identification and track reconstruction, effectively combining tracking and triggering capabilities in one single device. The present status of the full project will be reviewed, highlighting all importants steps and achievements since the start of the R& D in 2009. Several small and full-size prototypes were constructed with different geometries and techniques. The baseline design of the triple-GEM detector for CMS will be described, along with the results from extensive test measurements of all prototypes both in the lab and in test beams at the CERN SPS. The proposed on-and off-detector electronics for the final system will be presented.

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified.