J. DeWitt

The time slice system

Abstract We have designed a fast readout system for silicon microstrip detectors which could be used at HERA, LHC and SSC. The system consists of an analog amplifier-comparator chip (AACC) and a digital time slice chip (DTSC). The analog chip is designed in dielectric isolated bipolar technology for low noise and potential radiation hardness. The DTSC is built in CMOS for low power use and high circuit density. The main implementation aims are low power consumption and compactness. The architectural goal is automatic data reduction, and ease of external interface. The pipelining of event information is done digitally in the DTSC. It has a 64 word deep level 1 buffer acting as a FIFO and a 16 word deep level 2 buffer acting as a dequeue. The DTSC also includes an asynchronous bus interface. We are first building a scaled up (100 μm instead of 25 μm pitch) and slower (10 MHz instead of 60 MHz) version in 2 μm CMOS and plan to test the principle of operation of this system in the Leading Proton Spectrometer (LPS) of the ZEUS detector at HERA. Another very important development will be tested there: the radiation hardening of the chips. We have started a collaboration with a rad-hard foundry and with Los Alamos National Laboratories to test and evaluate rad-hard processes and the final rad-hard product. Initial data are very promising because radiation resistance of up to many Mrad have been achieved.

Signal-to-noise in silicon microstrip detectors with binary readout

We report the results of a beam test at KEK using double-sided AC-coupled silicon microstrip detectors with binary readout, i.e., a readout where the signals are discriminated in the front-end electronics and only the hit location as kept. For strip pitch between 50/spl mu/ and 200/spl mu/, we determine the efficiency and the noise background as function of threshold setting. This allows us to reconstruct the Landau pulse height spectrum and determine the signal/noise ratio. In addition, the threshold/noise ratio necessary for operation with low occupancy is determined. >

Tracker Readout ASIC for Proton Computed Tomography Data Acquisition

A unique CMOS chip has been designed to serve as the front-end of the tracking detector data acquisition system of a pre-clinical prototype scanner for proton computed tomography (pCT). The scanner is to be capable of measuring one to two million proton tracks per second, so the chip must be able to digitize the data and send it out rapidly while keeping the front-end amplifiers active at all times. One chip handles 64 consecutive channels, including logic for control, calibration, triggering, buffering, and zero suppression. It outputs a formatted cluster list for each trigger, and a set of field programmable gate arrays merges those lists from many chips to build the events to be sent to the data acquisition computer. The chip design has been fabricated, and subsequent tests have demonstrated that it meets all of its performance requirements, including excellent low-noise performance.

Beam tests of a double-sided silicon strip detector with fast binary readout electronics before and after proton-irradiation

Abstract A double-sided silicon strip detector with a radiation-tolerant design was fabricated and characterized in a sequence of beam tests at KEK using 4 GeV/ c pions. The detectors were combined with newly designed, fast, lower power, bipolar amplifier-shaper-discriminator chips and CMOS digital pipeline chips to record hit-no hit signals in the strips. Efficiencies, noise occupancies, and spatial resolutions were measured before and after the proton irradiation at an equivalent fluence of 1 × 10 14 p/cm 2 , depending on angle of track incidence and strip-pitches. The median pulse height distribution, derived from the threshold scans of the efficiency, allowed to extract the response of the detector. A 1 T magnetic field enabled us to determine the Hall mobilities of electrons and holes.

Beam Test Of The SDC Double-sided Silicon Strip Detector

A beam test was executed to evaluate the behavior of the first prototype radiation-hard double-sided silicon microstrip sensor for the SDC silicon tracking system. Pions of 4 GeV/c in a test bcamline at KEK illuminated three planes of detectors. Thc signals wcrc amplified, shaped, and discriminated with TEKZ bipolar analog LSIs, and the on-off levels were sampled at l0MHz clock with CMOS digiwl LSIs, asynchronously with beam triggers. The detectors were rotated in null and 1 .O Tesla magnetic fields. The efficiencies were found to be 98-9996. The position resolutions were 12.5pm. where the multi-strip hit fraction was 30-40%. There was no essential difference in the performance of the pand the n-sides. The multi-strip hit fraction showed a clear rotation and magnetic-field dependence. From the angles where the fractions were minimum in the 1T magnetic field, the Hall mobilities of the electrons and holes were obtained to be 1391k43 (clcctrons) and 325f30 (holes) cm2/Vs.

Monitoring the performance of silicon detectors with binary readout in the ATLAS beam test

The monitoring of the performance of silicon strip systems with binary readout is discussed. Due to the fact that neither pulse height nor noise level are recorded, the system is monitored with the efficiency and noise occupancy. As an example, on-line monitoring of the binary silicon strip system at the ATLAS H8 beam test at CERN is described.

Performance of the ATLAS silicon strip detector modules

Abstract The performance of the silicon strip detector prototypes developed for use in ATLAS at the LHC is reported. Baseline detector assemblies (“modules”) of 12 cm length were read out with binary electronics at 40 MHz clock speed. For both irradiated and unirradiated modules, the tracking efficiency, noise occupancy, and position resolution were measured as a function of bias voltage, binary hit threshold, and detector rotation angle in a 1.56 T magnetic field. Measurements were also performed at a particle flux comparable to the one expected at the LHC.

A fast tracker data acquisition system for pCT

We present a data acquisition design for a silicon-strip tracking system being constructed as part of a pre-clinical prototype scanner for proton computed tomography (pCT), capable of measuring one to two million proton tracks per second. The front end of the system is based on our ASIC design that handles 64 consecutive channels, including logic for control, calibration, buffering, and zero suppression. Each IC outputs a cluster list for each trigger, and a set of field programmable gate arrays merges those lists and builds the events to be sent to the data acquisition computer.