J.E. Franca

Intermittent polyphase SC structures for FIR rational interpolation

Rational sampling rate conversion factors L/M are usually obtained by cascading an L-fold upconverter followed by an M-fold downconverter. Because the traditional SC circuits employed in such cases give rise to undesired distortion effects due to the intermediary sampled-and-held signals, this paper proposes alternative solutions based on impulse sampled Intermittent Polyphase SC Structures that operate with either sampled-and-held or arbitrary input signal formats. Two alternative architectures are studied and their comparative advantages will be discussed from the viewpoints of component count and speed of the amplifiers. Behavioural level simulations illustrate well their discrete-time operation and the resulting input-output frequency responses.

A novel half-band SC architecture for efficient analog impulse sampled interpolation

The half-band filtering technique is an efficient approach especially for 2-fold sampling rate alterations. This paper proposes novel Switched-Capacitor (SC) architectures for sampled-data analog half-band impulse sampled interpolations whose system responses are also immune to the input sample-and-hold filtering effect distortion. Three alternative architectures are investigated with their corresponding comparative superiority from the viewpoints of required number of amplifiers and passive SC branches as well as clock phases. An effective multistage implementation of SC interpolation based on the newly proposed half-band interpolators is also described with further comparison among traditional designs.

Switched-capacitor finite impulse response interpolators without the input sample-and-hold filtering effect

This paper presents new Switched-Capacitor (SC) Finite Impulse Response (FIR) interpolators whose frequency responses are no longer affected by the input sample-and-hold filtering effect that occurred in previous circuits. Two different types of polyphase architectures are discussed, one based on the Direct-Form (DF) and another employing Active-Delayed Blocks (ADB). The DF polyphase structure is analysed either with input sampled-and-held signals or with arbitrary input signal formats, while the ADB structure is presented only with arbitrary input signal formats. Examples are given to illustrate both types of SC FIR interpolator circuits.

A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer

This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation achieved by Predictive Correlated-Double Sampling techniques. This filter is designed with optimized speed of the analog components in AMS 0.35 /spl mu/m CMOS technology, occupies about 0.4 mm/sup 2/ active area and consumes about 22 mW at 3.0 V supply.

New impulse sampled IIR switched-capacitor interpolators

This paper presents new Switched-Capacitor (SC) Infinite Impulse Response (IIR) Interpolators employing an efficient combination of Active-Delayed Blocks (ADB) polyphase structures and recursive direct-form II structures with frequency responses no longer affected by the input sample-and-hold filtering effect. Two different architectures are analysed: the first requires slower Operational Amplifiers (OAs) while the second allows the reduction of the number of clock phases and ADBs (1 OA per ADB). Examples are given to illustrate the behaviour of both types of SC interpolators with arbitrary input signal formats.

An SC CCIR-601 video restitution filter with 13.5 Msample/s input and 108 Msample/s output

This paper presents a design and implementation of a low-power switched-capacitor filter for NTSC/PAL digital video restitution system with CCIR-601 standards. The filter which employs optimized structures including coefficient-sharing, spread-reduction, semi-offset-compensation, mismatch-shaping, double-sampling and analog multirate and multistage techniques achieves linear-phase lowpass response with 5.5-MHz bandwidth, 108 Msample/s output from 13.5 Msample/s video input and active area about 3.3 mm/sup 2/ and about 80 mW power consumption. Behavior-, transistor- and layout-extracted level simulations are presented for illustrating the effectiveness of the circuit in 0.35 /spl mu/m CMOS technology.