J.G. Simmons

Theory of transient emission current in MOS devices and the direct determination interface trap parameters

Abstract The physics is discussed of the emission of electrons from interface states in metal-insulator-semiconductor (MIS) systems, under isothermal, non-steady-state conditions. Generalized equations are then derived which permit the determination of the non-steady-state, emission current vs time characteristics for MOS systems containing an arbitrary distribution of surface states; the special case of a discrete surface state is also studied. More important, however, by appropriate plotting of the data, it is shown how to directly extract from the experimental data the energy distribution and the capture cross section of the interface traps in the upper-half of the band gap in the case of n-type semiconductors, and in the lower-half of the band gap in the case of p-type semiconductors.

Theory of switching in p-n-insulator (tunnel)-metal devices: Part I: Punchthrough mode

Abstract The four-layered structure ( M - I (leaky)- n - p + ) is found to exhibit a current-controlled negative resistance region in its I-V characteristics. In this paper, a quantitative physical model of the device in the punch-through mode is presented. The negative resistance behaviour is due to a positive feedback mechanism between the tunnel MIS and the n - p + junction parts of the device. The effect of the device parameters on its I-V characteristics is studied.

Theory of dynamic charge current and capacitance characteristics in MIS systems containing distributed surface traps

Theoretical studies have been made on the dynamic characteristics of the metal-insulator-semiconductor (MIS) capacitor containing distributed surface traps. It has been shown that when the surface traps are in dynamic equilibrium with the voltage ramp, the device exhibits steady-state charge, current and capacitance characteristics. When the surface traps are out of equilibrium with the voltage ramp, then the emission of trapped charge is a function of time only and not of voltage. Under such conditions, the characteristics are considered to be non-steady-state in nature. In the steady state, the emission of electrons from a continuum of surface traps accounts for the reduction in the slopes of the C–V curves from the ideal ones. Kinks are manifested when the traps just empty the last of their electrons. In the non-steady state, electron emission can be described by the non-steady-state (time-dependent) occupancy function derived herein, which is shown to be similar in shape to the Fermi function. This means that electron emission takes place from a narrow band of energy positioned near the uppermost-filled traps. Hysteresis effects are manifested in the C–V characteristics due to the non-steady-state emission of trapped charge. At the transition from the steady state to the non-steady state and vice versa, kinks are exhibited in the charge and capacitance characteristics, while step changes in current components are also predicted. The physical processes involved have been stressed and closed-form expressions have been obtained for the charge, current and capacitance in terms of the trapping parameters, sweep-rate and temperature.

Theory of switching phenomena in metal/semi-insulator/n-p+ silicon devices

Abstract The theory of switching is presented for a structure consisting of a p + - n junction and a metal electrode separated from the N -section of the p + - n junction by a semi-insulating (leaky) layer. When a negative bias is applied to the electrode, the section of the n -layer under the electrode goes into deep depletion. In this mode, the current through the device is limited by generation in the deeply depleted region. This is the high-impedance or OFF state of the device. At a sufficiently high voltage, the switching voltage, V s , the p + - n junction is turned on by either avalanching in the n -layer or by the deep-depletion region extending through to the p + - n region (punch-through). When the junction turns on, the n -section goes from deep-depletion towards inversion. Thus, the voltage across the device decreases with a concomitant increase in the current through the device. This is the switching mode. The switching voltage may be tailored by varying the doping and/or width of the n -section. Following switching, the device comes into the steady-state when the current through the insulating layer is equal to the current flowing across the p + - n junction. The I-V characteristic of this highly conducting (ON state) mode is determined principally by the I-V characteristic of the semi-insulating film. By suitable choice of material this portion of the characteristic can approach zero dynamic impedance, i.e. a near-vertical characteristic, characterized by a low holding voltage. Capacitance and switching characteristics of the device are also discussed.

Theory of non-steady-state interfacial thermal currents in MOS devices, and the direct determination of interfacial trap parameters

Abstract Generalized equations are derived that permit the determination of the non-steady-state, thermal current vs temperature characteristics due to the emission of charge from interface states in MOS devices when the temperature increases uniformly with time. The equations are applicable to any trap distribution that extends over more than about 4kT in energy; the equations for discrete traps are also presented. The important result emerging from this work is that in the case of distributed traps the I−T characteristic is a direct reflection of the energy distribution of the interface traps. Furthermore, it is shown how the attempt-to-escape frequency ν of the traps and, hence, their capture cross-section may be determined. The determination of the trap density and energy and ν for discrete trap levels is also discussed.

Theory of dynamic charge and capacitance characteristics in MIS systems containing discrete surface traps

Abstract Theoretical studies have been made on the dynamic characteristics of the metal-insulator-semiconductor (MIS) capacitor containing discrete surface traps. It has been shown that when the surface traps are in dynamic equilibrium with the voltage ramp, the device exhibits steady-state charge and capacitance characteristics. When the surface traps are out of equilibrium with the voltage ramp, then the emission of trapped charge is a function of time only and not of voltage. Under such conditions, the characteristics are considered to be non-steady-state in nature. The emission of trapped charge in the non-steady state gives rise to a plateau or ledge in the C – V characteristics, while characteristics. The transition from the steady state to the non-steady state results in kinks in the characteristics. The physical processes involved have been stressed and simple expressions have been obtained for the charge and capacitance in terms of the trapping parameters, sweep-rate and temperature.

Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Abstract Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices. The device used here was an MNOS capacitor in which the semiconductor was n -type. The first technique which is described is that of measuring the thermally stimulated currents. The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface. The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps. The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored. The shape of the I−T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10 13 cm −2 eV −1 . The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical. The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface. It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored. The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique.

Experimental studies of switching in metal semi-insulating n-p+ silicon devices

Abstract The switching properties of silicon structures comprising a p + - n junction and a metal electrode separated from the n -section of the p + - n junction by a semi-insulating (leaky) layer are presented. Two basic types of structure were studied: devices with relatively light doped n -sections, and those with relatively heavily doped sections. The switching voltage of the first group was found to be proportional to the product of the doping density, N d and the square of the width of the n -section, and to be only very weakly temperature-dependent. The capacitance-voltage relationship of the device in the high-impedance mode was found to be of the form C −1 ∞ V 1 2 , and these measurements established that switching occurred just as the depletion region of the n -section under the gate electrode reached through to the p + - n junction. It was thus established that these devices were operating in the punch-through mode. In the second group of devices, the doping density of the n -section was increased by diffusing an n -well into the section. The switching properties were found to be quite different from the punch-through devices. The switching voltage was found to be independent of the width of the n -section and proportional to N d − 3 4 . Capacitance measurements also showed that the depletion region in the n -section under the oxide at switching, varied with the doping concentration, and was substantially less than the width of the n -layer. It was thus concluded that switching in these devices was of the avalanche-mode type.

Trapping, emission and generation in MNOS memory devices

This study is concerned with trapping phenomena occuring at the semiconductor-oxide interface and in the nitride layer of variable-threshold metal-nitride-oxide-semiconductor (MNOS) memory devices. The technique consits of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady mode that is quasi-stable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the I-T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy distribution of interface states is determied. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semi-permanent memory charge are distinguished.

Non-steady-state bulk-generation processes in pulsed metal-insulator-semiconductor capacitors

Abstract The non-steady-state bulk-generation process occurring in the pulsed metal-insulator-semiconductor (MIS) has been analyzed. During the early stages of relaxation to the quasi-equilibrium state the rate of generation of the electrons and holes are found to be time dependent and the two rates differ. Eventually, however, the two rates become time-dependent and equal to the steady-state generation rate. An analyses of Zerbst-type plots has been made in light of these results, and it is concluded that such plots are not necessarily indicative of the free-carrier lifetime, particularly if the voltage pulse is small or the trap density is high.