J. Kalisz

Interpolating time counter with 100 ps resolution on a single FPGA device

This paper describes the logic and performance of an interpolating time counter integrated on a single FPGA device. The resolution of 100 ps (LSB) was obtained because of the new design of the FPGA delay lines used for precise time-to-digital conversion, and the use of enhanced CMOS FPGA technology. The worst-case random error of 170 ps has been lowered to 70 ps by software correction of the nonlinearity of the delay lines. The counter can measure time intervals from 0-43 s and frequency up to 200 MHz. The maximum power consumption of the counter chip is 260 mW.

Single-chip interpolating time counter with 200-ps resolution and 43-s range

In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDCs nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS).

Error analysis and design of the Nutt time-interval digitiser with picosecond resolution

Several sources of errors related to the Nutt time-interval digitiser are discussed, including the quantisation process, time jitter, non-linearity of time stretchers and phase noise of the reference clock. A model of the total measurement uncertainty is formulated. The authors also describe the main circuitry and test results of a microprocessor-controlled digitiser which has been developed to achieve a negligible quantisation error (1 ps resolution) and 1 ms range.

Nonlinearity correction of the integrated time-to-digital converter with direct coding

A method is presented for automated identification and correction of the nonlinearity error of the time-to-digital converter (TDC) with delay-line coding and 200 ps resolution, integrated on a single Field Programmable Gate Array (FPGA) device. The nonlinearity error is estimated using a statistical method based on a sufficiently large number N of measurements of random input time intervals having a uniform distribution within the input range of TDC. Then, the resulting estimate of the error function is used for training a two-layer neural network (NN) designed for correction of the nonlinearity error. Training of the NN is based on the fast Levenberg-Marquardt (LM) learning rule and the goal is to minimize the maximum nonlinearity error of the TDC. Experimental tests have shown, that using a relatively small number of N=5/spl times/10/sup 4/ identification measurements the maximum nonlinearity error of a TDC may be reduced from 1.37 LSB (least significant bit) to about 0.12 LSB (24 ps).

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizers transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

Field programmable gate array time counter with two-stage interpolation

This paper presents a precise time counter with two two-stage interpolators, integrated in a field-programmable gate array device. Interpolation is performed by a single tapped delay line with dual synchronizers in the first stage and a differential tapped delay line in the second stage. The delay-locked loop is used for indirect stabilization of the propagation time of delay elements. The counter has 200ps resolution over the measurement range of 0–167ms with the standard measurement uncertainty below 140ps. A detailed analysis of influence of the flip–flop metastability on the counter accuracy is also presented.

PRECISION TIME COUNTER FOR LASER RANGING TO SATELLITES

A new design of the precision time counter for satellite laser ranging is described. The instrument features 3 ps incremental resolution within the measuring range up to 21.47 s, the short‐term rms error below 30 ps, and the time drift within ±5 ps. To reject unwanted noise and other disturbing signals the programmable window discriminator has been employed. In order to achieve high accuracy and good long‐term stability we used an automatic calibration based on the adaptive prediction. Further significant reduction of the measurement error has been achieved by self‐correction of the nonlinearity error and robust estimation. Results from experimental tests are presented to demonstrate the performance of the instrument.

A simple, precise, and low jitter delay/gate generator

The generator of precise delay over the range of 0–650 μs is described. The delay is selected with 10 ps resolution and its jitter is below 8 ps (rms) for delays up to 10 μs. The generator was designed as a complementary metal-oxide-semiconductor programmable logic device driven by a signal generator. Three output pulses are generated: START, STOP, and GATE, all with the amplitude of 2.3 V and the switching times below 500 ps.

A method for autocalibration of the interpolation time interval digitiser with picosecond resolution

A calibration method is described which allows precise determination of the stretch factors of the time stretchers used in the interpolation time interval digitiser with 1 ps incremental resolution. The method is based on analysis of statistical phenomena related to time jitter close to the threshold level of the phase detectors contained in the interpolators. The bias error inherent in the method is analysed and compensation of that error is discussed. A detailed description of a microprocessor procedure to perform automatic calibration is given. The usefulness of the method is proved by numerical examples and experimental results.

Improved time-interval counting techniques for laser ranging systems

Recent improvements in precision time-interval counting techniques are presented. Real-time autocalibration using an adaptive method for setting the optimum calibration rate, robust estimation of counter parameters, and input data filtering are discussed. The techniques described were evaluated during the development of time-interval counter T-1810B for satellite LRS in the Polish Academy of Sciences. Two adaptive calibration algorithms were tested, and results are presented. >