J. Lipovetzky

Electrically Erasable Metal–Oxide–Semiconductor Dosimeters

Metal-oxide-semiconductor (MOS) dosimetry including the reset of the sensor device for its reuse (reutilization) is described. The method consists in restoring the shifted threshold voltage after irradiation to a predefined value by the injection of a Fowler-Nordheim tunnel current. The amount of interface states per unit area is initially saturated in order to ensure repeatability. The method was tested on 70 nm pMOSFETs exposed to a 60Co source. After successive irradiations and erasures amounting several tens of kGy[SiO2], the devices exhibit a dispersion smaller than 2% in the responses.

Experimental evidence and modeling of two types of electron traps in Al2O3 for nonvolatile memory applications

Al2O3-based dielectrics are currently considered as promising materials to use in nonvolatile memories. The electron trap density in this material is much higher than in conventional SiO2, being their characteristics critical for the application. Conventional capacitance-voltage (C-V) techniques were used to study the main effects of the electron traps on the electrical characteristics of MOS capacitors with atomic layer deposited Al2O3 as insulating layer. More detailed information about the trapping kinetics was obtained through the study of the constant capacitance voltage transient. Two different types of traps were found. One is responsible for the instabilities observed in C-V measurements, the other has characteristic trapping times three orders longer. A physical model is presented to explain the observed trapping kinetics exhibiting good agreement between experiments and simulations. The energy levels of the studied traps were determined at 2.2 and 2.6 eV below the Al2O3 conduction band, with den...

Zero Temperature Coefficient Bias in MOS Devices. Dependence on Interface Traps Density, Application to MOS Dosimetry

In this paper the influence of temperature fluctuations on the response of thick gate oxide metal oxide semiconductor dosimeters is reviewed and the zero temperature coefficient (ZTC) method is evaluated for error compensation. The response of the ZTC current to irradiation is studied showing that the error compensation impoverishes with absorbed dose. Finally, an explanation and analytic expression for the shifts in the ZTC current with irradiation based on the interface traps creation is proposed and verified with experimental data.

Extension of the Measurement Range of MOS Dosimeters Using Radiation Induced Charge Neutralization

This work proposes a new biasing technique to extend the dose measurement range of MOS dosimeters. The technique consists on alternating stages of positive oxide charge buildup with stages of radiation induced charge neutralization, maintaining an uniform sensitivity along the whole measurement. The technique was applied with 70 nm MOS dosimeters, extending the dose measurement range from less than a kilogray to more than 675 kGy without showing wear effects. An initial saturation of interface traps creation ensures repeatability in the responses.

Reducing Measurement Uncertainties Using Bias Cycled Measurement in MOS Dosimetry at Different Temperatures

Temperature dependence of MOS dosimeters response used under the Bias Controlled Cycled Measurement technique is investigated. The use of the biasing technique allows the compensation of temperature-induced changes in the response of the sensors, and reduces at least ten times the dose measurement error caused by undesired threshold voltage shifts.

Field Oxide n-channel MOS Dosimeters Fabricated in CMOS Processes

This paper presents a new technique to build MOS dosimeters using unmodified standard CMOS processes. The devices are n-channel MOS transistors built with the regular Field Oxide as a thick radiation-sensitive gate. The devices were fabricated in two different commercial 0.6 μm CMOS processes, gate oxide thicknesses of ~600 nm and ~400 nm. Responsivities up to 4.4 mV/rad with positive bias, and 1.7 mV/rad with zero gate bias were obtained in the thicker oxides. The effect of charge trapped in the oxide and interface states on the shift in the threshold voltage are analyzed.

Floating Gate PMOS Dosimeters Under Bias Controlled Cycled Measurement

Floating Gate Metal Oxide Semiconductor (FG-MOS) structures, designed and fabricated in a CMOS process, were irradiated under the Bias Controlled Cycled Measurement (BCCM) novel technique conditions. Results presented in this work show the possibility of using such structures with the BCCM technique to measure ionizing radiation absorbed dose over a range of several kGy without significant loss of sensitivity. Transients observed after the bias switch are related to the evolution of the charge distribution between the floating gate and oxide traps near the semiconductor.

Commercial CMOS pixel array for beta and gamma radiation particle counting

We present the response of a Commercial-Off-The-Shelf (COTS) CMOS image sensor to different ionizing particles, with the aim of developing a low cost radiation detector. We first analyze the images obtained by exposing the imagers to X-rays from 55Fe, gamma and beta particles from 137Cs. Then the detector is successfully used to monitor different gamma fluxes produced by the RA6 nuclear research reactor, Argentina, during a startup procedure.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

This work proposes a novel methodology to evaluate SRAM-based FPGAs susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, TotalIonizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGAs VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGAs BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.

Switched Bias Differential MOSFET Dosimeter

This paper presents a differential MOSFET sensor reading technique based on the bias controlled cycled measurement. The circuit was implemented, and tested with gamma radiation from a 60-cobalt source. Temperature rejection performance was assessed during the exposure in real-time measurements. The results show that in comparison with a single MOSFET dosimeter the thermal drift is 20 times smaller and the radiation sensitivity is approximately 10% higher. The switched biasing allows to extend the measurement range beyond MOSFETs threshold voltage saturation.