J. Maalmi

High resolution photon timing with MCP-PMTs: A comparison of a commercial constant fraction discriminator (CFD) with the ASIC-based waveform digitizers TARGET and WaveCatcher

There is considerable interest to develop new time-of-flight detectors using micro-channel-plate photomultiplier tubes (MCP-PMTs). The question we pose in this paper is whether available waveform digitizer ASICs, such as the WaveCatcher or TARGET, operating with a sampling rate of 2–3 GSa/s, can compete with 1GHz BW CFD/TDC/ADC electronics. We have performed a series of measurements with these waveform digitizers connected to MCP-PMTs operating at low gain and with a signal equivalent to ∼40 photoelectrons. These tests were performed using a laser diode to illuminate the photodetectors under conditions comparable to those used in previous SLAC and Fermilab beam tests. Our measurement results indicate that one can achieve similar timing resolution with both methods. Although commercial CFD-based electronics are readily available and perform very well, they are impractical for large scale systems. In contrast, ASIC-based waveform recording electronics are well-suited to such applications, and do not require analog delay lines that otherwise make CFDs difficult to incorporate in ASIC designs.

The WaveCatcher family of SCA-based 12-bit 3.2-GS/s fast digitizers

The recent progresses in detector developments have raised the requirements for the associated readout electronics. High-end oscilloscopes are well adapted for test and characterization setups, but their cost per channel is high and their number of channels very limited. Precision test benches can also make use of ADC-based fast digitizers, but most of these modules are expensive and the most performing house very few channels. The recent progress of high speed Switch Capacitor Arrays (SCA) now permits offering sampling rates far above 1 GHz over 12 bits at low cost and low power consumption. The WaveCatcher board family has thus been developed for proposing an alternative to ADC-based digitizers (or even oscilloscopes). It is based on the SAMLONG SCAs developed since 2010 with the AMS CMOS 0.35-μm technology. All boards offer a wide DC-coupled dynamic range of 2.5 V (with adjustable offset) coded over 12 bits, a bandwidth of 500 MHz and a sampling rate ranging between 0.4 and 3.2 GS/s, which allows them to finely sample high speed signals like very short pulses. The sampling depth is of 1024 samples. The number of channels goes from 2 for the USB-powered version packaged in a friendly plastic box to 64 (optionally 72) for the version housed in an autonomous mini-crate. Thanks to the servo-controlled matrix structure of SAMLONG and the care taken in the board design, the sampling time precision is of the order of 5 ps rms, which permits using the system as a high-resolution TDC between any pair of channels, as this precision remains constant between chips and boards. The boards offer a lot of functionalities, like threshold-triggering on any channel and numerous trigger modes including coincidence. All system versions house a 480-Mbits/s USB interface permitting an easy connection to PC and a good readout speed. In parallel to hardware and firmware developments, we developed a powerful and user friendly acquisition software running on PC and transforming the latter into a 2 to 64-channel oscilloscope. It permits saving data files directly on disk, and is currently used in most WaveCatcher system applications. An increasing number of labs or companies are now using the WaveCatcher boards worldwide on their test benches or physics experiments.

Picosecond time measurement using ultra fast analog memories

The currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The constant fraction technique minimizes the time walk effect (dependency of timing on the pulse amplitude). Several attempts have been made to integrate CFD in multi-channel ASICs. But the time resolution measured on the most advanced one is of the order of 30 ps rms. Two main techniques are used for the TDC architectures. The first one makes use of a voltage ramp started or stopped by the digital pulse. The obtained voltage is converted into digital data using an Analog to Digital Converter (ADC). The timing resolution of such a system is excellent (5 ps rms). But this technique is limited by its large dead time which can be unacceptable for the future high rate experiments. Another popular technique associates a coarse measurement performed by a digital counter with a fine measurement (interpolation) using Delay Line Loop. Such a system can integrate several (8-16) channels on an FPGA or an ASIC. The most advanced DLL-based TDC ASIC exhibits a timing resolution of 25 ps, but only after a careful calibration. It should be noticed that the overall timing resolution is given by the quadratic sum of the discriminator and of the TDC. In the meantime, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit achieving a timing resolution far better than the sampling frequency. For example, 100ps rms resolution has been reported for a signal sampled at only 100MHz. Digitization systems have followed the progress of commercial ADCs, which currently offer a rate of 500 MHz over 12 bits. Their main drawbacks are the huge output data rate and power consumption. Their packaging, cooling, and tricky clock requirements also makes them very hard to implement. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new USB-WaveCatcher board has been designed to provide high performances over a short time window. It houses on a small surface two 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAM chip, an analog circular memory of 256 cells per channel. Its innovative matrix design permits reaching these performances, yet in a cheap pure CMOS 0.35µm technology, while consuming only 300 mW. Raw sampling precision is as good as 15ps rms. In an embodiment where the clock is directly sent to the SAM chip, thus limiting the usable sampling frequency to 3.2GHz, and after a calibration of the fixed pattern time distribution, a reproducible time precision of a few ps has been demonstrated. The board also offers various functionalities. Its input offset is tunable over a range of 2 V. It can be triggered either internally or externally and several boards can easily be synchronized. Trigger rates counters are implemented. Both channels can also be used for reflectometry thanks to their internal pulser. The precision obtained for cable length measurements is as good as 2mm. Charge measurement mode is also provided, through integrating on the fly over a programmable time window the signal coming for instance from photo-multipliers. Power consumption is only 2.5 W which permits powering with the sole USB. Signal connectors can be BNC, SMA or LEMO. The board houses a USB 12 Mbits/s interface permitting a dual-channel readout speed of 500 events/s. Faster readout modes are also available. In charge measurement mode, the sustained trigger rate can reach a few tens kHz. A 480Mbits/s version will soon be available. Various evolutions of the SAM chip are under study, targeting either higher precision time measurements or longer time window. The USB-WaveCatcher can thus replace oscilloscopes for a much lower cost in most high-precision short-window applications. Moreover, it opens new doors into the domain of very high precision time measurements.

The SAMPIC Waveform and Time to Digital Converter

SAMPIC is a Waveform and Time to Digital Converter (WTDC) multichannel chip. Each of its 16 channels associates a DLL-based TDC providing a raw time with an ultra-fast analog memory allowing fine timing extraction as well as other parameters of the pulse. Each channel also integrates a discriminator that can trigger itself independently or participate to a more complex trigger. After triggering, analog data is digitized by an on-chip ADC and only that corresponding to a region of interest is sent serially to the DAQ. The association of the raw and fine timings permits achieving timing resolutions of a few ps rms. The paper describes the detailed SAMPIC0 architecture and reports its main measured performances.

Trigger architecture of the SuperNEMO experiment

SuperNEMO is the next-generation (0νββ) experiment based on a tracking plus calorimetry technique. The demonstrator is made of a calorimeter (712 channels) and a tracking detector (6102 channels). These detectors front-end electronics use an unified architecture. The calorimeter and tracker can operate separately. We have an overlap between the zoning of the calorimeter and the tracker. The final trigger decision is made considering spatial coincidences between hits from the calorimeter and tracker detectors.

SamPic0: A 16-channel, 10-GSPS WTDC digitizer chip for picosecond time tagging

SamPic0 is a Waveform Time to Digital Converter (WTDC) multichannel chip providing outstanding time measurement capabilities. It makes use of the AMS 0.18-μm CMOS technology. One of its specificities stands in its capacity to directly measure the arrival time of fast analog signals without the need of any external discriminator. Each of its 16 channels associates a traditional DLL-based TDC providing a raw time based on a counter and a DLL associated with an ultra-fast 64-cell deep analogue memory (bandwidth > 1.5 GHz, sampling frequency > 10GS/s) allowing fine timing extraction as well as other parameters of the pulse like charge, pulse width or rise-time. Each channel also integrates a discriminator that can self-trigger the channel independently or allows it to participate to a more complex trigger embedded on-chip. External trigger is also available. After triggering, analogue data is also digitized on-chip by massively parallel low-power 11-bit Wilkinson ADCs running at 1.3 GHz and only data corresponding to a predetermined region of interest is then transferred towards the acquisition system. Dead-time is thus limited to 1.6 μs for an 11-bit conversion and is as low as 400 ns for a 9-bit conversion which already provides an excellent time precision. Contrasting with the existing fast sampler chips usually designed for all-purpose applications and requiring external electronics to be used for performing accurate timing measurements, the SAMPIC0 chip presented here has been specifically designed for the latter type of application. Although the SAMPIC0 chip was originally thought as a technological demonstrator, its readout has been structured for low dead-time applications and its design thus permits an easy integration in medium size acquisition systems. Such a set of boards and DAQ system has already been developed with the primary goal of evaluating the chip performances, but it is also usable to take data with detectors in a real environment. This setup, including a powerful software with an original interactive graphical interface, has permitted the characterization of the SAMPIC0 chip, and the measurements of its time resolution which is as good as 14 ps rms without any time correction. This value is decreased in the range of 3 to 4 ps rms after a simple correction, itself based on a very simple calibration. This calibration remains very stable with time and can thus be stored on-board. This paper will present the new WTDC concept, the chip architecture, the existing set of boards and DAQ system and will give report of the latest measurements of the chip performances. It will also present the modifications and additions to the design of the second version of the chip, which should be submitted in 2014.

Electronics for the SuperNEMO experiment, with focus on Control and ReadOut

SuperNEMO (SN) is the next-generation neutrinoless double beta decay (0νββ) experiment based on a tracking plus calorimetry technique. The construction of the demonstrator module has started in 2013 and its installation is expected in 2014 in LSM underground laboratory (France). The SN experiment is designed to measure both energy and time of flight of each beta particle emitted from ββ decays.The demonstrator is made of a calorimeter detector (712 channels) associated to a tracking detector (6102 channels). These detectors front-end electronics use an unified architecture based on six similar crates that each host up to 20 Front-End Boards (FEB) and 1 Control board (SN_CROB). The FEBs perform the acquisition of the detector channels. The SN_CROB board gathers the front-end data from the calorimeter or tracker FEBs and sends them through Ethernet link to the data acquisition (DAQ) system. It extracts the Trigger Primitive (TP) from the front-end data and sends them through serial link to the Trigger Board (SN_TB). Moreover the SN_CROB board distributes the clock, the trigger and the control signals for all the boards in a crate. It can also provide its own clock.

Cherenkov detector for proton flux measurement for UA9 project

A report about the development of a device called Cherenkov detector for proton flux measurement is presented. This device is going to be installed first in the Super Proton Synchrotron and later at Large Hadron Collider collimation area to monitor of the secondary beam, produced by a bent crystal inserted in the proton halo. By measuring the number of Cherenkov light produced by the protons in the quartz radiator we expect less the 10% precision in particle counting, for around 100 incoming protons. Geant4 based simulation and first tests with 446 MeV electron beam are discussed.