J. Manjula

Low Power Low Noise Tunable Active Inductor for Narrow Band LNA Design

paper presents a low power, low noise and high quality factor tunable single ended active inductor suitable for designing multiband RF front end circuits. The active inductor circuit uses differential configuration as positive transconductor and PMOS cascode structure as negative transconductor of a gyrator to reduce the noise voltage. It uses MOS transistor as a feedback resistor to provide possible negative resistance to reduce the inductor loss to enhance the quality factor. Also this structure provides wide inductive bandwidth and high resonance frequency. The tuning of center frequency and quality factor for multiband operation is achieved through the controllable current source. The center frequency tuning range of the active inductor varies from 3.9 GHz to 12.3 GHz. The designed active inductor and LNA are simulated in 180nm CMOS process using HSPICE simulation tool. Simulation results of the active inductor shows an inductive bandwidth varies from 6.45 MHz to 6.3 GHz with the center frequency 6.3 GHz. The inductance value ranges from 5nH to 550nH respectively. It has the less noise voltage of 12nV/√Hz to 5.6nV/√Hz for the designed tuning range and consumes less power of 0.65mW. The Low noise amplifier achieves the gain of 19dB, low noise figure of 2.1dB and consumes low power of 4.2mW. Keywordsinductor, Quality factor, Centre frequency tuning, PMOS cascode pair, tuning range, MOS resistor, Multiband RF front end.

Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.

Design of low power high speed SAR based 16-bit analog to digital converter: Charge sharing approach

This paper presents a high speed low power successive approximation register (SAR) based analog-to-digital converter (ADC) using Charge-Sharing (CS) principle. SARs critical path plays a vital role in high speed application of ADCs. A 16-bit SAR array with reduced critical path delay is proposed to obtain delay of 60ps, along with charge-sharing ADC incorporated with low-voltage low-power double-tail comparator (LV-LPDTC), is proposed in 45nm CMOS to convert 10 MSps at 600 mV supply voltage and 40MSps when supply voltage raised by 66.67%. The SAR controller array consumed 16.47 μW, which leads to a overall power consumption of 149.1 μW. The measured effective-number-of-bits is 15.1, confined to a FoM of 70.76 fJ/conversion-step.

Design of VCO with harmonic extraction circuits

This paper presents a design of LC tank circuit using current mirror that achieves tuning range of 23.17% and Phase noise of -85dBc/Hz with a power consumption of 50uW for a power supply of 5V. The harmonics produced from VCO are extracted by using band pass filter (BPF) and amplified using common gate amplifier and cascode amplifier and differential buffer produces doubler output. The proposed design is simulated using 90nm technology in Cadence Virtuoso Analog Design Environment tool.

Multiband HEMT low noise amplifier for 2 to 5 GHz

This paper presents 2 to 5 GHz Multiband Low Noise Amplifier (LNA) using a HEMT technology for multiband receiver. The circuit is designed using an inductively-degenerated cascode topology with voltage shunt feedback to improve the gain and noise figure of the LNA. The designed LNA exhibits a forward transfer gain S21 above 12dB, Noise Figure (NF) of less than 1.5 dB and input reflection coefficient S11 below -10dB across a 2-5 GHz band with a supply voltage of 3V.

Design of 60 GHz GaAs LNA

Low-power 60 GHz low-noise amplifier (LNA) with a 9.379 dB peak gain and a 4.500 dB minimum NF is demonstrated in a GaAs Based technology. The LNA is composed of three stage of cascaded common-source stages with inductive degeneration technique. The 1st stage of common-source given to the input stage for simultaneous noise and input matching. Also, the further stages is used for gain enhancement and interstage/output matching. This LNA consumes only 0.005 W from a 1 V supply.

Design of 5 GHz microstrip line based RF subsystem

In this paper, performance analysis of Microstrip based RF subsystems such as impedance transformer, and low noise amplifiers (LNA) are presented in 180 nm CMOS technology employing MS (microstrip) transmission lines. The frequency of operation is 5 GHz. The impedance transformer is designed using coupled microstrip lines for better impedance matching providing return losses of -24.819dB. A modified cascode MS-LNA with current reuse is proposed for gain boosting. The proposed LNA serves a maximum gain 16.444dB and moderate noise figure of 1.415. The software used is Advance Designing Software (ADS).