J. Moron

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

A fast, low-power, 6-bit SAR ADC for readout of strip detectors in the LHCb Upgrade experiment

The readout of silicon strip sensors in the upgraded Tracker System of Large Hadron Collider beauty (LHCb) experiment will require a novel complex Application Specific Integrated Circuit (ASIC). The ASIC will extract and digitise analogue signal from the sensor and subsequently will perform digital processing and serial data transmission. One of the key processing blocks, placed in each channel, will be an Analogue to Digital Converter (ADC). A prototype of fast, low-power 6-bit Successive Approximation Register (SAR) ADC was designed, fabricated and tested. The measurements of ADC prototypes confirmed simulation results showing excellent overall performance. In particular, very good resolution with Effective Number Of Bits (ENOB) 5.85 was obtained together with very low power consumption of 0.35 mW at 40 MS/s sampling rate. The results of the performed static and dynamic measurements confirm excellent ADC operation for higher sampling rates up to 80 MS/s.

Performance of fully instrumented detector planes of the forward calorimeter of a Linear Collider detector

Detector-plane prototypes of the very forward calorimetry of a future detector at an e+e- collider have been built and their performance was measured in an electron beam. The detector plane comprises silicon or GaAs pad sensors, dedicated front-end and ADC ASICs, and an FPGA for data concentration. Measurements of the signal-to-noise ratio and the response as a function of the position of the sensor are presented. A deconvolution method is successfully applied, and a comparison of the measured shower shape as a function of the absorber depth with a Monte-Carlo simulation is given.

Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz – 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps – 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 μm × 210 μm, while the same circuit designed in process B occupies 430 μm × 190 μm.

Development of low-power high speed (10Gb/s) drivers in CMOS 130 nm technology

The aim of this work is to develop a dedicated low power transmitter interface for high-speed data transmission in CMOS 130 nm technology. Such interface is necessary in complex ASICs working at high frequencies and processing large amounts of data, in particular it is needed in advanced detector readout systems of particle physics experiments. New multichannel readout ASICs, capable to transmit data at high frequencies (>5Gb/s), with low jitter, and consuming very low power, are recently being intensively developed. A Current Mode Logic (CML) and Source-Series Terminated (SST) interfaces are natural candidates to drive the data out of the chip. A broadband extension techniques using inductors may be applied to extend the bandwidth of these drivers. Unfortunataly, inductors occupy very large area what limits their applications in ASICs. In this work the CML driver using inductive peaking and two SST drivers (with, without series peaking) were developed to achieve transmission speeds between 5-10 Gb/s, together with very low (<;2 ps) jittter. We present and compare the schematic and post-layout simulations of the developed drivers together with all relevant parameters (speed, jitter, eye diagram). Prototype designs in CMOS 130 nm were already submitted and are now in fabrication.

IOP : 8-channel prototype of SALT readout ASIC for Upstream Tracker in the upgraded LHCb experiment

SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Upstream Tracker of the LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of an analogue front-end and an ultra-low power (<0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. An 8-channel prototype (SALT8), comprising all important functionalities was designed, fabricated and tested. A full 128-channel version was also submitted. The design and test results of the SALT8 prototype are presented showing its full functionality.

Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC for Readout of Particle Physics Detectors

The design and measurement results of an ultra-low power multi-channel fast 10-bit Analog-to-Digital Converter (ADC) ASIC, developed for readout systems in future particle physics experiments, are discussed. An 8-channel prototype with a PLL-based data serialization and a fast data transmission was designed and fabricated in a 130 nm CMOS process. The ADC converts analog data with sampling rates from about 10 kS/s to 40 MS/s, with power consumption proportional to sampling rate. The resulting Figure of Merit (FOM), for sampling rates 5-40 MS/s, is 35-42 fJ/conv.-step, per ADC channel. Similar power contribution is spent for fast data serialization and the largest contribution goes to data transmission. A wide spectrum of static and dynamic measurements confirm very good performance of this multi-channel ADC with ENOB ~9.2 bits, an excellent channel uniformity, and negligible crosstalk. The ADC works asynchronously and so it is not limited to systems with uniform time sampling. The ADC is designed using dynamic circuitry which eliminates static power consumption (except leakage), as a consequence it is ready for applications requiring power cycling.

Development of radiation-hard bandgap reference and temperature sensor in CMOS 130 nm technology

A stable reference voltage (or current) source is a standard component of todays microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, which show correct operation (<;1mV bandgap stability, linear PTAT) in teperature range -20 to 100 celsius degree.

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block—VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz–3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz).