J. Pineda de Gyvez

Analog fault diagnosis based on ramping power supply current signature clusters

Measurement of power supply currents was found to be very useful for testing CMOS ICs because of its potential to detect a large class of manufacturing defects. However, this technique was used mainly for fault detection and was confined to digital circuits. In this paper, we present a suited methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all possible regions of operation by using a ramp signal at the supply instead of the conventional constant DC signal or ground voltage. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit.

DNA computing based on chaos

In this paper a new approach for the realization of the DNA computing paradigm is presented. It exploits the natural richness of chaotic dynamics to efficiently generate and process coded binary sequences following the DNA computing framework introduced by Adleman (1994). The new method is discussed and some simulation results regarding the Directed Hamiltonian Path problem are presented.

Time-multiplexing CNN simulator

A novel approach to simulate Cellular Neural Networks (CNN) is presented in this paper. The approach, time-multiplexing simulation, is prompted by the need to simulate hardware models and test hardware implementations of CNN. For practical size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware processors and all the pixels of the image. This simulator provides a solution by processing the input image block by block, with the number of pixels in a block being the same as the number of CNN processors in the hardware. The algorithm for implementing this simulator is also presented, along with some simulation results and comparisons.<<ETX>>

A power supply ramping and current measurement based technique for analog fault diagnosis

Presents a methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all regions of operation by using a ramp signal at the supply instead of the conventional constant dc signal. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit.<<ETX>>

Time-domain analog wavelet transform in real-time

This paper presents a time-domain approach for the implementation and continuous generation of wavelet transform coefficients. The wavelet generation relies on amplitude modulation techniques. This approach offers two extra degrees of freedom through the appropriate use of the modulation index and the selected envelope signal. The added flexibility opens the possibility to create new families of wavelets which are specially suitable for analog implementations. The theoretical fundamentals for the generation of wavelets using the amplitude modulation scheme are presented. Simulated and experimental results for our hardware prototype are presented.

Full-signature real-time corrosion detection of underground casing pipes

Corrosion monitoring and early detection of pits and wall thinning for casing pipes are considerably important to gas and petroleum industries since the frequently occurring corrosion at the internal or external parts of those steel casing pipes used in underground gas storage or oil fields causes production and environmental protection problems. In this paper, a new version of the direct current (dc) electromagnetic induction system is introduced in which a sensor system, based on the dc electromagnetic induction instrument, is coupled with an updated data acquisition system. Unlike the conventional dc induction instrument, the new system can achieve a full-signature logging response by providing all the measured flux leakage (FL) signals and eddy current (EC) signals to the computer logging system (CLS) on the surface. To transmit the information represented by large amounts of data acquired by downhole instruments to the CLS on the surface, a wavelet data compression technique has been incorporated. A VLSI integrated circuit (IC) which realizes the wavelet transform has been designed so that the real-time mode can be achieved during the logging operation. The circuit has been designed using CMOS n-well 2-/spl mu/m technology and has been fabricated by MOSIS.

A Four Quadrant S2I Switched-Current Multiplier

Switched-current (SI) circuits [164] represent a feasible alternative to switchedcapacitor (SC) [102,165] circuits especially due to their compatibility with digital technology.

Analog fault diagnosis: a fault clustering approach

A novel analog circuit fault diagnosis method is proposed. This method uses a neural network paradigm to cluster different faults. It is capable of dealing with the common fault models in analog circuits, namely the catastrophic and parametric faults. The proposed technique is independent of the linearity or nonlinearity of the circuit. The process parameter drifts and component tolerance effects of the circuit are well taken care of. Several fault diagnosis strategies for different problem complexities are described. The proposed methodology is illustrated by means of an operational transconductance amplifier (OTA) example.<<ETX>>

Filtering and spectral processing of 1-D signals using cellular neural networks

This paper presents cellular neural networks (CNN) for one-dimensional discrete signal processing. Although CNN has been extensively used in image processing applications, little has been done for 1-dimensional signal processing. We propose a novel CNN architecture to carry out these tasks. This architecture consists of a shift register, e.g., a charge coupled device, and a 1/spl times/n neural array. Each cell processes a sample of the input signal. By using appropriate templates and shifting the input signal the CNN array is capable of performing FIR filtering, discrete Fourier transform, and wavelet decomposition and reconstruction. Even though this implementation is not more efficient than conventional methods, the paper shows that an analog computer based on the CNN paradigm can also be used to perform the linear operations described above. Simulation results and comparisons for spectral audio applications are presented.

Frequency-domain intrachip communication schemes for CNN

A frequency-domain scheme to share a communications channel among the cells of a CNN is proposed. The scheme is based on a modification of the wave-parallel-computing technique and addresses the problem of reducing the number of communication links. Reduction in the communication paths is achieved by frequency multiplexing. This makes it possible to have simultaneous full-parallel access to all the cells of the array. The approach also takes advantage of the parallelism inherent in wave-parallel-computing to solve part of the state equation within the same channel during a transmission operation. Moreover, with this architecture, the CNN array is not required to have a physical matrix array of cells, providing in this form even more flexibility for the hardware implementation. A system level simulation was done and operating ranges were found as an aid to propose a final system architecture of a tentative VLSI IC.