J. Price

Spectroscopic ellipsometry characterization of HfxSiyOz films using the Cody–Lorentz parameterized model

A parameterized, Kramers–Kronig consistent, Cody–Lorentz optical model is used to simulate the dielectric response of thin HfxSiyOz films. Optical constants are determined in the range 0.75–8.35eV. The Cody–Lorentz model has three specific differences when compared to the previously employed Tauc–Lorentz model: (1) weak exponential absorption below the band gap, (2) a modified joint density-of-states, and (3) a restriction on the e1(∞) parameter. These three differences allow the Cody–Lorentz model to have an improved fit to experimental data. As a result of a more accurate optical model for HfxSiyOz, we were able to identify an interfacial layer with thickness in close agreement with transmission electron microscopy measurements. Use of the Tauc–Lorentz model when fitting the same experimental data could not identify an interfacial layer. Results are also discussed in which the Cody–Lorentz model shows sensitivity to varying degrees of silicate composition.

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

We present the first demonstration of a III–V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III–V and Si devices can be processed side by side in the same Si fabrication line The L<inf>g</inf> = 500 nm device has a excellent drive current of ∼450 µA/µm and intrinsic transconductance of ∼1000 µS/µm indicating that III–V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Origin of the Flatband-Voltage Roll-Off Phenomenon in Metal/High-

The effect of flatband-voltage reduction [roll-off (R-O)], which limits fabrication options for obtaining the needed band-edge threshold voltage values in transistors with highly scaled metal/high- k dielectric gate stacks, is discussed. The proposed mechanism causing this R-O phenomenon is suggested to be associated with the generation of positively charged oxygen vacancies in the interfacial SiO2 layer next to the Si substrate. The vacancies in the interfacial layer are induced by oxygen outdiffusing into the overlying high-k dielectric. The model is consistent with the variety of observations of R-O dependence on the electrode and substrate type, high-k dielectric composition and thickness, temperature, etc. The models predictions were experimentally verified.

k

Spectroscopic ellipsometry is used to characterize charge trapping defect states in thin HfO2 gate dielectric films deposited by atomic layer deposition on chemically oxidized p-type Si (100) substrates. The intensity of specific absorption features detected below the band gap of HfO2 at 2.9 and 4.75eV is clearly distinguished from the Si critical points; however, repeating this spectroscopic evaluation for identical HfO2 films deposited and annealed on fused silica substrates results in no defect features detected. The HfO2∕Si(100) results, therefore, suggest these oxygen deficient defects are not intrinsic to HfO2 but reside primarily at the interface with the silicon substrate. The feasibility of utilizing spectroscopic ellipsometry to identify stoichiometric variations at the SiO2∕Si(100) interface and the corresponding changes associated with the electrical performance is presented.

Gate Stacks

The authors present a spectroscopic study of defects in HfO2, Hf0.8Si0.2O2, Al2O3, and SiO2 dielectric gate stacks. The results indicate that all optically observable dielectric-related defects are associated with the interfacial SiO2 layer rather than the bulk high-k film. The identified defects, located at 2.9, 3.5, 3.9, and 4.75eV within the dielectric film’s band gap, are found to be strongly affected by subsequent postdeposition anneal treatments and trend consistently with recent electron spin resonance results and theoretical calculations of optical transitions associated with negatively charged vacancies in SiO2 media. The close connection between our results and both atomistic calculations and experimental findings motivates the use of spectroscopic ellipsometry as a potential in-line characterization method for identifying process-induced defects during complementary metal oxide semiconductor device fabrication.

Identification of sub-band-gap absorption features at the HfO2∕Si(100) interface via spectroscopic ellipsometry

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN_x trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaV_t = 4V with respect to the initial state are obtained. The band-engineered SiN_x charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.

Identification of interfacial defects in high-k gate stack films by spectroscopic ellipsometry

Hard x-ray photoelectron spectroscopy (HAXPES) was performed on In0.53Ga0.47As/Al2O3 gate stacks as deposited and annealed at 400 °C, 500 °C, and 700 °C to test for out-diffusion of substrate elements. Ga and As core-level intensities increase with increasing anneal temperature, while the In intensity decreases. HAXPES was performed at two different beam energies to vary the surface sensitivity; results demonstrate Ga and As out-diffuse into the Al2O3 film. Analysis suggests the presence of an interlayer containing Ga and As oxides, which thickens with increasing anneal temperature. Further diffusion, especially of Ga, into the Al2O3 film is also observed with increasing anneal temperature.

Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

In a previous study, we demonstrated that the BeO film grown by atomic layer deposition (ALD) on Si and III-V metal-oxide-semiconductor devices has excellent electrical and physical characteristics. In this paper, we discuss the physical and electrical properties of ALD BeO as an oxygen diffusion barrier on scaled 4-nm HfO2/BeO gate stacks. Thin BeO layers are deposited onto (100) p-Si substrates as an alternative to SiO2 as an interfacial passivation layer (IPL). X-ray photoelectron spec troscopy and transmission electron microscopy show that the BeO IPL acts as an effective oxygen barrier against SiOιι. native oxide formation during postdeposition annealing (PDA). The use of ALD BeO as an oxygen diffusion barrier results in lower equivalent oxide thickness, more competitive leakage current, and better reliability characteristics after PDA than Al2O3 and HfO2 gate stacks.

Hard x-ray photoelectron spectroscopy study of As and Ga out-diffusion in In0.53Ga0.47As/Al2O3 film systems

The authors investigated the optical and electrical properties of the high permittivity (κ) metal oxides, HfTiO and HfTaTiO, using HfO2 as a reference and compared their material properties against their electrical performance. HfTiO has a higher κ value but its band offset is relatively smaller and, therefore, it has greater gate leakage current than HfO2. HfTaTiO has an even higher κ value which compensates for the impact of its small band offset. In addition, HfO2 was found to have more defect states than the other two films, which caused a larger hysteresis in the capacitance-voltage scan and degraded channel mobility.

Epitaxial ALD BeO: Efficient Oxygen Diffusion Barrier for EOT Scaling and Reliability Improvement

We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC