J. Schulze

Vertical tunnel field-effect transistor

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.

Electrical spin injection and transport in germanium

We report the first experimental demonstration of electrical spin injection, transport, and detection in bulk germanium (Ge). The nonlocal magnetoresistance (MR) in n-type Ge is observable up to 225 K. Our results indicate that the spin relaxation rate in the n-type Ge is closely related to the momentum scattering rate, which is consistent with the predicted Elliot-Yafet spin relaxation mechanism for Ge. The bias dependence of the nonlocal MR and the spin lifetime in n-type Ge is also investigated.

A vertical MOS-gated Esaki tunneling transistor in silicon

Abstract For the first time a vertical, MOS gated tunneling transistor in silicon is fabricated. The necessary sharp doping profile structure is created by means of MBE. Pronounced transistor action due to Esaki tunneling is demonstrated at room temperature. At a low supply voltage of −0.2 V a current gain of three magnitudes with saturation behaviour is achieved. MOS-gate, low supply voltage and exponential current increase make this device attractive for ULSI applications.

Electrically pumped lasing from Ge Fabry-Perot resonators on Si

Room temperature lasing from electrically pumped n-type doped Ge edge emitting devices has been observed. The edge emitter is formed by cleaving Si-Ge waveguide heterodiodes, providing optical feedback through a Fabry-Perot resonator. The electroluminescence spectra of the devices showed optical bleaching and intensity gain for wavelengths between 1660 nm and 1700 nm. This fits the theoretically predicted behavior for the n-type Ge material system. With further pulsed electrical injection of 500 kA/cm2 it was possible to reach the lasing threshold for such edge emitters. Different lengths and widths of devices have been investigated in order to maintain best gain-absorption ratios.

GeSn/Ge multiquantum well photodetectors on Si substrates

Vertical incidence GeSn/Ge multiquantum well (MQW) pin photodetectors on Si substrates were fabricated with a Sn concentration of 7%. The epitaxial structure was grown with a special low temperature molecular beam epitaxy process. The Ge barrier in the GeSn/Ge MQW was kept constant at 10 nm. The well width was varied between 6 and 12 nm. The GeSn/Ge MQW structures were grown pseudomorphically with the in-plane lattice constant of the Ge virtual substrate. The absorption edge shifts to longer wavelengths with thicker QWs in agreement with expectations from smaller quantization energies for the thicker QWs.

Tuning the Ge(Sn) Tunneling FET: Influence of Drain Doping, Short Channel, and Sn Content

We present experimental results on the realization of p-channel mode Ge(Sn) heterojunction band-to-band tunneling field effect transistors. We investigate the influence of three device parameters (drain doping, channel length, and tunnel barrier height at source side) of the semiconductor body of the devices on the device performance. We achieve a complete suppression of the n-channel mode in p-type operating conditions by systematically reducing the p-type drain doping from 1·1020 to 2 · 1017 cm-3, examined in sample series A. In the second sample series B, we investigate the influence of a reduction of the channel length down to 15 nm on transistor performance. To improve the ON current ION without degrading the OFF current IOFF, we introduce a 10-nm delta layer of a Ge1-xSnx alloy at the source/channel junction in the third sample series C. We demonstrate an improved ON current ION compared with the reference sample without a GeSn delta layer.

Gate-controlled resonant interband tunneling in silicon

We present gate-controlled resonant interband tunneling on silicon ⟨111⟩. The investigated structure principally consists of a vertical, gated p-i-n diode grown by molecular beam epitaxy. We evaluated the surface tunnel current from a gate-induced two-dimensional electron channel into the quantized hole states of a degenerately doped δp+ layer. This current reveals a negative differential resistance due to resonant interband tunneling in the forward biased p-i-n diode at 200K. Even at room temperature the influence of this tunnel mechanism is observed. The experimental results are in good agreement with simulated band diagrams and their dependence on the applied voltages.

Hanle-effect measurements of spin injection from Mn5Ge3C0.8/Al2O3-contacts into degenerately doped Ge channels on Si

We report electrical spin injection and detection in degenerately doped n-type Ge channels using Mn5 Ge 3C0.8/Al2O3/n+ -Ge tunneling contacts for spin injection and detection. The whole structure is integrated on a Si wafer for complementary metal-oxide-semiconductor compatibility. From three-terminal Hanle-effect measurements, we observe a spin accumulation up to 10 K. The spin lifetime is extracted to be 38 ps at T = 4 K using Lorentzian fitting, and the spin diffusion length is estimated to be 367 nm due to the high diffusion coefficient of the highly doped Ge channel.

Vertical power-MOSFETs with local channel doping

In this work we present a new vertical approach for solving the tradeoff between breakdown capability and on state resistance for PowerMOS devices. We use a vertical transistor on an epitaxial layer. This concept allows the adjustment of the breakdown voltage due to the thickness of the epi-layer separately from the on-state resistance, which is defined by the vertical transistor. The transistor was fabricated by means of atomic layer deposition, which allows very small channel length and doping control on atomistic scale. Devices with breakdown voltages between 12 V and 40 V were fabricated. It is also shown that local channel doping (/spl delta/-doping) instead of homogenous doping in the switching transistor reduces the on state resistance of the device significantly.

Boron surface phase on Si(111): atomic structure and Si overgrowth studied by scanning tunneling microscopy and work function measurement

Abstract Surface reconstructions of boron (B) on silicon (Si) have been well known for several years. One reconstruction of special interest to us is the so called 3 × 3 − R30° boron surface phase (BSP) on Si(111). This reconstruction can occur in two different forms, one with B located on T4 lattice sites (B-T4), the second one with B residing in S5 sites (B-S5) directly underneath a Si adatom in a T4 site. The two forms of the 3 × 3 − R30° reconstruction are expected to exhibit completely different properties due to their different chemical binding. In this paper we present work function measurements of these surface phases which clearly show their distinctively different behaviour and allow the determination of the temperature at which the boron atoms migrate from the T4 sites to the S5 sites. Furthermore, STM results concerning the overgrowth of BSPs with Si films of variable thicknesses and its effect on the BSP itself are shown.