J. Selvakumar

FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter

The scope of the paper is to design a new Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, which are designed for symmetric coefficients that aim at reducing hardware cost in our design with a constraint that the filter tap must be a multiple of 2. The reduction in area is achieved by replacing the adder by a bulky multiplier. For example, for a 4 parallel 36-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a four-parallel 288-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.

Efficient Complexity Reduction Technique for Parallel FIR Digital Filter based on Fast FIR Algorithm

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure with the constraint that the filter tap must be a multiple of 2. In our work we have briefly discussed for L = 4 parallel implementation. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. For example, for a 6-parallel 1024-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a six-parallel 512-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.

High gain and low power design of preamplifier for CMOS comparator

In this paper, a low power and low noise preamplifier is designed for Analog to Digital Converter (ADC) operating with 1.2 V power supply. The pre-amplification technique is based on differential pair with cascode stage which provides very low power. The goal of achieving high gain and low power is achieved by operating the circuit in differential mode to get maximum gate to source voltage. The gain of feedback loop also helps to attain high gain. The proposed pre-amplifier is simulated in 90nm CMOS technology. The open loop DC gain of proposed pre-amplifier is 32 dB, the gain bandwidth product is 108 kHz with a phase margin of 62 degrees. The power consumption of proposed pre-amplifier is 3.3 μW for 1.2 V power supply.

Adaptive FIR Filter to Compensate for Speaker Non-linearity

In this paper we have implemented an adaptive filter to compensate for the non-linearity in a speaker. An attempt has been made to minimize the Mean Square Error (MSE) and convergence time using the LMS adaptive algorithm. Two adaptations of the LMS have been considered, the general adaptive LMS algorithm and the Leaky LMS algorithm. The Leaky LMS adaptation is observed to be more efficient with almost a 40 % decrease in convergence time. The filter coefficients for the above objective function are obtained using MATLAB. The target processor for implementing the two algorithms is Tensilica/Xtensa SDK toolkit using ‘C’ language which enables the codes to be directly dumped on to hardware.