J. Torres

Advanced copper interconnections for silicon CMOS technologies

Interconnects for advanced semiconductor devices are facing increasingly difficult challenges. Several material alternatives are being investigated in order to meet very strict requirements. Currently, copper is the most widely accepted material for advanced metallization. This article gives a general overview of the world-wide R&D effort underway to develop both manufacturable processes and their integration at each level of the interconnect structure. For each basic step, the state of the art is presented, with particular focus on the results obtained within the European Copper Interconnection Project (COIN).

Copper Photocorrosion Phenomenon during Post CMP Cleaning

During post‐chemical mechanical polishing (CMP) cleaning of copper Damascene structures by diluted hydrofluoric acid , a corrosion phenomenon has been shown on patterned wafers, leaving a copper deposit and an associated copper etching. Methods are developed to eliminate the phenomenon by use of benzotriazole or crotonic acid in the diluted solutions. At the same time,the presence of these inhibitors does not change the cleaning efficiency of the diluted solutions. Also, the elimination of light during the cleaning step eliminates the corrosion. A theoretical explanation is given. ©2000 The Electrochemical Society

Ultra thin diffusion barriers for Cu interconnections at the gigabit generation and beyond

Abstract The reliability of copper interconnection depends on the barrier effectiveness of conductive or non-conductive layers to block any copper motion. The conductive barrier materials currently used in Al-based interconnections — Ti, TiN, W and nitrided W — have been investigated as barrier against copper diffusion. The barrier thickness must be as thin as possible to achieve negligible barrier contribution to the total line resistance. Electrical tests C-V on MOS capacitors were performed to assess the rate of electrically active copper impurities transported through the barrier layer. The stability of a copper/barrier/oxide/silicon structure was studied under thermal stress with or without bias. For back-end process annealing performed under vacuum, the copper diffusion was shown to be limited, and very thin barrier films were shown to be effective in preventing copper diffusion.

Electromigration resistance of copper interconnects

Abstract Copper has been suggested as a promising interconnect material for ULSI applications, because of the low resistivity of copper compared to aluminum. Due to decreasing interconnect and contact dimensions, a high electromigration resistance of the metallization material is required. Electromigration tests were performed in the course of the european COIN project on copper interconnects with linewidths between 1 and 4 μm and different sample preparations. The copper was deposited by CVD or PVD methods. Patterning was done by ion milling or RIE. TiN or TiW were used as a barrier. Tests were performed at wafer level and package level in the temperature range from 170°C to 250°C and current densities from 2 MA/cm2 to 15 MA/cm2. Activation energies between 0.60 and 1.00 eV were determined depending on the deposition and patterning method and the used barrier. A comparison between the different copper samples and a standard AlSiCu is presented showing a 10-fold improvement in lifetime.

Film texture evolution in plasma treated TiN thin films

In semiconductor technology, TiN thin film elements can be used as diffusion barrier between a metallic layer and a silicon oxide dielectric. Plasma application during the growth of TiN thin films modifies the microstructure of these films and consequently alters their physical properties. But details of the effect of plasma application on the evolution of the film microstructure and correlations between this evolution and the physical properties are still unclear. To clarify the correlations, the microstructure of a series of TiN thin films, deposited using an organometallic chemical vapor deposition technique combined with plasma treatments has been analyzed by transmission electron microscopy (TEM). The films were obtained by repeated fabrication sequences consisting of limited film growth followed by the application of a N2/H2 gaseous plasma with various powers and duration times and are actually stackings of plasma-treated elementary layers. TEM analysis shows that these films are made of nanocrystallites and that whereas crystallites are randomly oriented when no plasma is applied, short-time plasma treatments induce a tendency to 〈200〉 texture and longer treatments progressively rotate the direction of texture to 〈220〉.In semiconductor technology, TiN thin film elements can be used as diffusion barrier between a metallic layer and a silicon oxide dielectric. Plasma application during the growth of TiN thin films modifies the microstructure of these films and consequently alters their physical properties. But details of the effect of plasma application on the evolution of the film microstructure and correlations between this evolution and the physical properties are still unclear. To clarify the correlations, the microstructure of a series of TiN thin films, deposited using an organometallic chemical vapor deposition technique combined with plasma treatments has been analyzed by transmission electron microscopy (TEM). The films were obtained by repeated fabrication sequences consisting of limited film growth followed by the application of a N2/H2 gaseous plasma with various powers and duration times and are actually stackings of plasma-treated elementary layers. TEM analysis shows that these films are made of nanocrystal...

TiN-CVD process optimization for integration with Cu-CVD

Abstract Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter- and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu/SiO 2 interconnection structures. After a review of the TiN-CVD performance as a diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu/TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/Cu-CVD process integration.

Ti-diffusion barrier in Cu-based metallization

Abstract Reliability investigations, with or without a barrier layer, have been performed to study the penetration of copper into thermal oxide as a function of temperature and applied electric field. No copper diffusion was detected without a barrier into 100 nm thick oxide for temperature stress as high as 450°C for one hour and for bias temperature stress (BTS) as high as 300°C for 8 h at 1 MV/cm. This absence of diffusion was observed when thermal annealing was performed under vacuum. A 20 nm thick titanium layer was used as a diffusion barrier/adhesion promoter between the copper and the oxide. The devices using this barrier were not affected by a temperature stress of 600°C for 10 h and by BTS even at 450°C for 2 h at 1 MV/cm.

Copper-based metallization for ULSI circuits

The feasibility of copper metallization for interconnections in ultra-large scale integrated circuits is under evaluation in the ESPRIT/JESSI project COIN (Copper INterconnections). Research has been performed comprising all basic aspects of copper metallization for integrated circuits, such as development and evaluation of processes for metal deposition and patterning, evaluation of materials which could act as barrier against copper diffusion, electrical testing of the barrier layer performance and finally evaluation of the electromigration performance of copper interconnections.

Study of Cu contamination during copper integration for subquarter micron technology

Abstract Copper contamination in several dielectric deposited on copper-CVD film was investigated. This study aims at integrating copper in a dual damascene structure interconnection for sub-quarter micron technology. A complete contamination profile into the deposited dielectric was available using SIMS, TXRF (total X-ray reflection fluorescence) and LPD–AAS (liquid phase decomposition–atomic absorption spectroscopy) as complementary characterization tools. The Cu contamination profile of the SiN/SiO2 and SiO2 structure deposited on copper was given. The PECVD process used for both process cleaning of the chamber and SiOF deposition imply plasma with fluorine and the reactivity of this species with copper was shown to be critical for dielectric contamination and copper contact surface. Eventually, a cleaning solution was investigated to lower the contamination at the surface of the dielectric, the most contaminated part.

TEM studies of the microstructure evolution in plasma treated CVD TiN thin films used as diffusion barriers

Abstract In semi-conductor technology, TiN thin films elements are used as diffusion barriers between a copper interconnect layer and a silicon oxide dielectric. Plasma treatment application, by modifying the film microstructure, can improve the film barrier properties and its electrical conductivity. But details of the plasma application effect on the film microstructure evolution and correlations of this evolution with the physical properties are still unclear. To clarify the correlations, the microstructure of a series of TiN thin films deposited using an OMCVD (organo-metallic chemical vapor deposition) technique has been analyzed by transmission electron microscopy (TEM). The films were obtained by cycling a basic synthesis sequence including first a limited film growth and then application of a N2/H2 gaseous plasma with various powers and duration times. Films are actually stackings of plasma-treated elementary layers. TEM analyses show that films are made of nanocrystallites and that whereas no texture is observed when no plasma is applied, short-time plasma treatment induces a tendency to 〈100〉 texture and if treatment is longer, the direction of texture progressively rotates to 〈110〉. A tentative interpretation of this texture evolution has been made in terms of nucleation and growth and correlations between this evolution and the effect on the physical properties have been obtained.