J. Vasi

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFETs using a novel charge pumping (CP) technique. The technique directly provides separate N/sub it/ and N/sub ot/ profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N/sub it/ and N/sub ot/ profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N/sub it/ generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N/sub it/ profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N/sub it/) and oxide (N/sub 0t/) traps in hot-carrier stressed MOSFETs. Direct separation of N/sub it/ and N/sub 0t/ is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms.

Experimental observation of avalanche multiplication in charge-coupled devices

Avalanche multiplication of signal charge in surface-channel charge-coupled devices is reported in this paper. Experimental observations show that avalanche multiplication takes place when the electrons are made to fall down a steep barrier of more than 8 V in an overlapping gate structure. For a 16-V fall, the gain in charge is about 3-percent per transfer. A simple model is developed which explains the experimental data reasonably well. The upper limit to the amplitude of clock voltages that can be applied to a CCD is likely to be determined by this avalanche multiplication mechanism rather than the oxide breakdown criterion.

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.

A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs

Abstract A new charge pumping (CP) technique is proposed to obtain the spatial profile of interface-state density ( N it ) and oxide charges ( N ot ) near the drain junction of hot-carrier stressed MOSFETs. Complete separation of N it from N ot is achieved by using a direct noniterative method. The pre-stress CP edge is corrected for the charges associated with both the generated N it and N ot . A closed form model is developed to predict the stress-induced incremental CP current. The damage distributions are obtained after fitting the model with experimental data.

The nature of intrinsic hole traps in thermal silicon dioxide

The energy and spatial distribution of intrinsic hole traps in dry thermal silicon dioxide have been determined. Thermal detrapping was used for the determination of energy levels of the traps and the etch‐back technique was used to find the spatial location of the traps. These traps are distributed in energy from 1.0 to 1.5 eV with respect to the valence band edge of the silicon dioxide. Their centroid is located at approximately 120 A from the Si–SiO2 interface. Results of various postoxidation annealing treatments show that the density of traps is significantly dependent on the process conditions. Like fixed charge Qf, these traps seem to be related to the lattice imperfections in SiO2 near the interface; however, the hole trap density and Qf vary in opposite directions due to the process changes. N2 annealing increases the trap density and O2 annealing, which reduces the hole trap density, increases the electron trap density in SiO2. Based on these results we support the trivalent silicon model for th...

Visual Degradation in Field-Aged Crystalline Silicon PV Modules in India and Correlation With Electrical Degradation

This paper presents the analysis of visual degradation data collected during an All-India Survey of Photovoltaic Module Degradation conducted in 2013, in which 57 crystalline silicon modules were inspected in the five different climatic zones of India. Analysis of the data indicates that the highest percentage of modules suffered discoloration in the Hot and Dry climatic zone, with the Hot and Humid zone coming in second in the list. A higher percentage of modules have suffered corrosion in the Hot and Humid zone, as compared with other zones. The modules installed in the Cold climate suffered the least degradation. Both discoloration and corrosion have been seen in modules across all age groups, even in some of the modules installed less than five years ago. On the other hand, delamination and backsheet degradation have been seen only in modules more than a decade old. The visual degradation data have been correlated with the electrical performance data and reaffirm the direct relation between encapsulant discoloration and reduction in short-circuit current and output power, as well as that of series resistance with metal corrosion.

Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.

A numerical simulation of hole and electron trapping due to radiation in silicon dioxide

The one‐dimensional Poisson, continuity, and the trap rate equations are solved numerically to study the buildup of charge in silicon dioxide due to radiation. The flat‐band voltage shift (ΔVfb) is obtained as a function of total dose, the oxide thickness, the applied gate voltage, and the centroid of the trap distribution. The effect of including electron traps is studied. The results of the simulation are found to compare well with experimental data.

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N+) to Si-rich ( Si+) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant over erase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si+ SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si+ SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND flash applications.