J.W. Walker

PHENIX inner detectors

Abstract The timing, location and particle multiplicity of a PHENIX collision are determined by the Beam–Beam Counters (BBC), the Multiplicity/Vertex Detector (MVD) and the Zero-Degree Calorimeters (ZDC). The BBCs provide both the time of interaction and position of a collision from the flight time of prompt particles. The MVD provides a measure of event particle multiplicity, collision vertex position and fluctuations in charged particle distributions. The ZDCs provide information on the most grazing collisions. A Normalization Trigger Counter (NTC) is used to obtain absolute cross-section measurements for p–p collisions. The BBC, MVD and NTC are described below.

PHENIX central arm particle ID detectors

Abstract The Ring-Imaging Cherenkov (RICH) and the Time-of-Flight (ToF) systems provide identification of charged particles for the PHENIX central arm. The RICH is located between the inner and outer tracking units and is one of the primary devices for identifying electrons among the very large number of charged pions. The ToF is used to identify hadrons and is located between the most outer pad chamber (PC3) and the electromagnetic calorimeter. A Time Zero (T0) counter that enhances charged particle measurements in p–p collisions is described. Details of the construction and performance of both the RICH, ToF and T0 are given along with typical results from the first PHENIX data taking run.

Monolithic circuits for the WA98 lead class calorimeter

Two monolithic circuits developed for readout of a 10000 element lead glass calorimeter are described. The first contains 8 channels with each channel comprising a charge integrating amplifier, two output amplifiers with gains of one and eight, a timing filter amplifier and a constant fraction discriminator. This IC also contains a maskable, triggerable calibration pulser and circuits needed to form 2 by 2 and 4 by 4 energy sums used to provide trigger signals. The second IC is a companion to the first and contains 16 analog memory channels with 16 cells each, eight time-to-amplitude converters and a 24-channel analog-to-digital converter. The use of the analog memories following the integration function eliminates the need for delay cables preceding it. Characterizations of prototypes are reported, and features included to ease integration of the ICs into a readout system are described.<<ETX>>

Ring imaging Cherenkov detector of PHENIX experiment at RHIC

Abstract The RICH detector of the PHENIX experiment at RHIC is currently under construction. Its main function is to identity electron tracks in a very high particle density, about 1000 charged particles per unit rapidity, expected in the most violent collisions at RHIC. The design and construction status of the detector and its expected performance are described.

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 /spl mu/s ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ n-well CMOS process used for preamplifier fabrication.

A flexible analog memory address list manager for PHENIX

A programmable analog memory address list manager has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 105 ns. Addresses are handled such that up to 5 Level-1 (LVL-1) events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam-event data packets. Full usage in all PHENIX analog memory-based detector subsystems is accomplished by the use of detector-specific programmable parameters-the number of data samples per valid LVL-1 trigger and the sample spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including application specifics, timing information, and test results from a full implementation using field programmable gate arrays (FPGAs).

A multiplicity-vertex detector for the PHENIX experiment at RHIC

Abstract A Multiplicity-Vertex Detector (MVD) has been designed, and is in construction for the PHENIX Experiment at the Relativistic Heavy Ion Collider (RHIC). The 35 000 channel silicon detector is a two-layer barrel comprised of 112 strip detectors, and two disk-shaped endcaps comprised of 24 wedge-shaped pad detectors. The support structure of the MVD is very low mass, only 0.4% of a radiation length in the central barrel. The detector front-end electronics are a custom CMOS chip set containing preamplifier, discriminator, analog memory unit, and analog-to-digital converter. The system has pipelined acquisition, performs in simultaneous read/write mode, and is clocked by the 10 MHz beam crossing rate at RHIC. These die, together with a pair of commercial FPGAs that are used for control logic, are packaged in a mutlichip-module (MCM). The MCM will be fabricated in the High-Density-Interconnect (HDI) process. The prototype MCM design layout is described.

Development of a front end controller/heap manager for PHENIX

PHENIX FEMs have three classifications: Type I A controllerheap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

A front-end electronics module for the PHENIX pad chamber

A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The modules control functions are performed by the heap manager unit, an FPGA-based circuit on the FEM. Each FEM processes signals from 2160 channels of front-end electronics (FEE). Data readout and formatting are performed by an additional FPGA-based circuit on the FEM. Three external systems provide initialization, timing, and data information via serial interfaces. This paper discusses the application of the heap manager, data formatter, and serial interfaces to meet the specific control and data readout needs of the Pad Chamber subsystem. Unit functions, interfaces, timing, data format, and communication rates are discussed. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling and FPGA implementation and programming are presented.

The PHENIX ring imaging Cherenkov detector

Abstract The PHENIX experiment at RHIC is primarily a lepton and photon detector. Electron detection takes place in the two central arms of PHENIX, with the primary electron identifier in each arm being a ring imaging Cherenkov detector. This paper contains a description of the two identical RICH detectors and of their expected performance.