Jacques Henri Collet

Architectural approach to the role of Optics in monoprocessor and multiprocessor machines

The relevance of introducing optical interconnects (OIs) in monoprocessors and multiprocessors is studied from an architectural point of view. We show that perhaps the major explanation for why optical technologies have nearly been unable to penetrate into computers is that OIs generally do not shorten the memory-access time, which is the most critical issue for todays stored-program machines. In monoprocessors the memory-access time is dominated by the electronic latency of the memory itself. Thus implementing OIs inside the memory hierarchy without changing the memory architecture cannot dramatically improve the global performance. In strongly coupled multiprocessors the node-bypass latency dominates. Therefore the higher the connectivity (possibly with optics), the shorter the path to another node, but the more expensive the network and the more complex the structure of electronic nodes. This relation leaves the choice of the best network open in terms of simplicity and latency reduction. The bottlenecks resulting from and the benefits of implementing OIs are discussed with respect to symmetric multiprocessors, rings, and distributed shared-memory supercomputers.

Numerical approach to non-equilibrium carrier relaxation in picosecond and subpicosecond physics

Abstract We present a numerical resolution of the time-dependent Boltzmann equation which describes the electron relaxation kinetics in direct gap semiconductors under subpicosecond optical excitation. The calculation is specialized to GaAs. We investigate, around the Mott density, the conditions of internal thermalization and energy relaxation of electrons, which depend strongly on the plasma concentration.

Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays

We study chip self-organization and fault tolerance at the architectural level to improve dependable continuous operation of multicore arrays in massively defective nanotechnologies. Architectural self-organization results from the conjunction of self-diagnosis and self-disconnection mechanisms (to identify and isolate most permanently faulty or inaccessible cores and routers), plus self-discovery of routes to maintain the communication in the array. In the methodology presented in this work, chip self-diagnosis is performed in three steps, following an ascending order of complexity: interconnects are tested first, then routers through mutual test, and cores in the last step. The mutual testing of routers is especially important as faulty routers are disconnected by good ones with no assumption on the behavior of defective elements. Moreover, the disconnection of faulty routers is not physical (“hard”) but logical (“soft”) in that a good router simply stops communicating with any adjacent router diagnosed as defective. There is no physical reconfiguration in the chip and no need for spare elements. Ultimately, the multicore array may be viewed as a black box, which incorporates protection mechanisms and self-organizes, while the external control reduces to a simple chip validation test which, in the simplest cases, reduces to counting the number of valid and accessible cores.

Hot spots and core-to-core thermal coupling in future multi-core architectures

This paper studies hot spot and thermal coupling problems in future multicore architectures as CMOS technology scales from 65 nm feature size to 15 nm. We demonstrate that the thermal coupling between neighboring cores will dramatically increase as the technology scales to smaller feature sizes. The simulation studies were based on solving the heat equation using the analytical Greens function method. Our simulations indicate that the thermal coupling in the 15 nm feature size just after 100 ms of operation will increase from 20% to 42% and in the steady state might reach even 65%. This finding uncovers a major challenge for the design of future multi-core architectures as the technology keeps scaling down. This will require a holistic approach to the design of future multi-core architectures encompassing low power computing, thermal management technologies and workload distribution.

Production Yield and Self-Configuration in the Future Massively Defective Nanochips

We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore architectures and 2) the issue of preserving the production yield. Our main suggestion is that the chip should be self-configuring at the architectural level, enabling with almost no external control mechanisms, core mutual-test to isolate the defective core and self-configuration of communications to discover the routes in the defective network. Our contribution is a systematic study of the dependence of the production yield versus the core failure probability (possibly as high as 0.4) in several networks with different node connectivity ranging from 3 to 5. The result is obtained in terms of a probabilistic metrics to warrant that a minimal fraction of nodes can be contacted by the input-output port for participating to the processing.

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

We start with a detailed analysis of the communication issues in todays symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines. We show that the transmission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data duplicated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a difficult challenge for shared electric buses. In this context we suggest the introduction of simple point-to-point OIs for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function. The operation might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of transmissions to preserve a large bandwidth and a short memory access latency. The interest for OIs comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involving more optical technology. This solution allows multiple simultaneous accesses to the bus, but the preservation of the coherence of caches can no longer be maintained with the usual fast snooping protocols.

ROBUST: a new self-healing fault-tolerant NoC router

This work addresses the general problem of making Network-on-Chips (NoCs) routers totally self-healing in massively defective technologies. There are three main contributions. First, we propose a new hardware approach based on Built-In Self-Test techniques and multi-functional blocks (called Universal Logic Blocks, ULBs) to autonomously diagnose permanent faults and repair faulty units. ULBs have the capability to assume the functionality of various functional units within the router through simple reconfiguration and thus enable the repair of multiple permanent faults within the NoC router. Second, we propose a new reliability metric and introduce a probabilistic model to estimate the router reliability improvement achieved by the protection circuitry. Third, we compare our architecture to two router architectures (Vicis and Bulletproof) and we show that our design provides superior reliability improvement especially in extremely defective nanoscale technologies (i.e., typically above 30% of faulty routers). The most striking result is that the self-healing of the routers enables maintaining the communications at fault levels, where it is normally impossible to preserve communications.

Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips

The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the architectural level in multiport processor grids (MPG) through core dual diagnosis and self-configuration of communications. MPGs are considered to ensure the scalability of future hundred-core chips. We characterize defective technologies by the IOP reachability (i.e., the ability of the IOPs to contact a fraction of cores in the grid) that we study as a function of the fraction of defective cores or links. We show that almost all valid cores in the grid are accessible by all input-output ports (IOP) up to approximately 20-25% of defective cores. This property is quasi-independent of the position of the IOPs in the grid.

Mitigating soft errors to prevent a hard threat to dependable computing

This paper presents first the context and motivation for dealing with soft errors. In order to be able to account for the various issues involved, a concerted reflection has been carried out including embedded system integrators, manufacturers, and academic researchers. The authors have summarized the main outcomes of this effort. Finally, the various contributions that are meant to address the several factors that characterize the problem posed by soft errors and provide solutions was introduced to mitigate their effects.

Optical Bus versus Electronic Bus for Address-Transactions in Future SMP Architectures

The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP) build around shared busses. This kind of multiprocessor is especially attractive because the problem of data coherency in caches can be solved by a class of snooping protocols specific to these shared-bus architecture. But the bandwidth demand, especially for the addresses, is becoming so important that a technological step must be considered. Optical communications are becoming mature and bring a huge information bandwidth through the implementation of optical busses. This paper is focused on the address bandwidth needed by shared-bus SMP without suggesting a complete solution. We show that an optical address bus can fulfil the bandwidth demand of future SMPs contrarily to standard electronic busses.