Jaehyun Baek

Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture

This paper proposes a new simplified degree computationless modified Euclids algorithm (S-DCME) and its architecture for Reed-Solomon decoders. The proposed S-DCME algorithm uses the new initial conditions, and thus, it can combine the data path for loading initial values and the data path for a switching operation. Hence, the S-DCME algorithm can reduce the number of multiplexers and has high performance compared with the existing DCME algorithm and the RiBM algorithm. The gate count using the MagnaChip HSI 0.25mum standard cell library is 17,800.

A continuous flow mixed-radix FFT architecture with an in-place algorithm

The paper proposes a fast Fourier transform (FFT) architecture to satisfy both small area and high speed. The proposed architecture uses the mixed-radix algorithm based on the radix-4 and radix-2 algorithms and the memory bank structure for high speed real-time processing. To satisfy the small area requirement, it uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. To meet real-time processing, this paper proposes a continuous flow architecture using only two N-word memories for the mixed-radix algorithm. The proposed architecture can reduce the number of clock cycles about 70% compared with an existing architecture.

Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder

This paper proposes an enhanced degree computationless modified Euclids (E-DCME) algorithm for Reed-Solomon decoder. The critical path delay of the proposed E-DCME algorithm requires only TMul + T ADD + TMUX. In addition, the proposed E-DCME algorithm can reduce the used basic cells and has the latency of 2t -1 clock cycles for solving the key equations. Hence, the proposed E-DCME algorithm has short critical path delay and small area compared with the conventional modified Euclids algorithm (ME) and the existing DCME algorithm. The gate count of the proposed E-DCME architecture is 17,840. Therefore, the E-DCME architecture can reduce the gate count about 18% compared with the existing DCME architecture

New in-place strategy for a mixed-radix FFT processor

This paper proposes a fast Fourier transform (FFT) processor using a new in-place strategy and the mixed-radix algorithm. The proposed processor uses only two N-word memories for a continuous flow FFT implementation, due to the new in-place strategy, while existing continuous FFT processors use four N-word memories. In addition, the proposed processor satisfies both small area and real-time processing requirement. The gate count of the processor is 37,000 and the number of clock cycles is 640 for a 512-point FFT. Hence, the proposed FFT processor can reduce the gate count and memory size compared with existing FFT processors.

Low hardware complexity key equation solver chip for Reed-Solomon decoders

This paper proposes a new simplified degree computationless modified Euclids algorithm (S-DCME) and its architecture for Reed-Solomon decoders. The proposed S-DCME algorithm reformulates the existing modified Euclids (ME) algorithm and uses new initial conditions to remove unnecessary hardware components and to use simple data paths. Thus, it requires two less multipliers and t + 2 less multiplexers compared with the reformulated inversionless Berlekamp-Massey (RiBM) algorithm which has shown the best performance so far. The critical path delay of S-DCME is 7.92 ns, i.e., TMul + TADD + TMUX, that is equal to that of RiBM. The gate count of the implemented chip using the MagnaChip HSI 0.25 mum standard cell library is 17,800.

Novel digital signal processing unit for Ethernet receiver

The paper proposes a novel digital signal processing (DSP) unit for an Ethernet receiver. The proposed DSP unit consists of a programmable gain amplifier (PGA), a timing recovery, a new adaptive equalizer, and a proposed baseline wander (BLW) compensator. The proposed adaptive equalizer uses 2/sup -7/ as the optimum step size, i.e., /spl mu/. Since the optimum step size is a multiple of 2, the equalizer can eliminate multipliers. Hence, the proposed equalizer has small area and consumes low power. In addition, the proposed BLW compensator implemented in a digital domain uses four symbols, including the present symbol, and can remove BLW at the channel having large BLW. To verify the performance, we simulate the proposed DSP unit using the SPW/sup /spl trade// tool. The implemented DSP unit using the 0.18 /spl mu/m SEC cell library operates at 142.7 MHz and consists of 128,528 gates. The measured BER is less than 10/sup -10/ when the transmitted data is received up to 150 m.