Jaewoo Park

Impact of Oxygen Flow Rate on the Instability Under Positive Bias Stresses in DC-Sputtered Amorphous InGaZnO Thin-Film Transistors

The effect of O2 flow rate (OFR) during channel deposition is investigated on the electrical instability of the amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under positive gate bias stresses. From the transfer curves measured before and after bias stresses, we can observe that the high OFR degrades the electrical stability and causes the large threshold voltage shift (ΔVT) in a-IGZO TFTs. To elucidate the origin of the observed phenomenon, we extract and compare the subgap density of states (DOS) in devices with various OFRs. The extracted DOS shows that the subgap states become higher with the increase of OFR in a wide range of bandgap, and the enhanced electron trapping due to the increased number of trap states is considered as the cause of larger ΔVT in higher OFR devices.

Molecular orbital ordering in titania and the associated semiconducting behavior

RF-sputtered TiOx layers were thermally treated and the associated thin-film transistor properties were studied. X-ray diffraction and x-ray absorption spectroscopy analyses indicate that as-grown amorphous TiOx films crystallize to anatase at temperatures above 450 °C in air. Thin-film transistors incorporating anatase active layers exhibit n-type behavior, with field effect mobility values near 0.11 cm2/Vs when annealed at 550 °C. Such a phenomenon is suggested to originate from the ordering of Ti 3d orbitals upon crystallization, and the mobility enhancement at higher annealing temperatures may be attributed to the reduced grain boundary scattering of carriers by virtue of enlarged average grain size.

Relation Between Low-Frequency Noise and Subgap Density of States in Amorphous InGaZnO Thin-Film Transistors

The relation between the low-frequency noise (LFN) and subgap density of states (DOS) of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is investigated by changing the postannealing temperature from 150°C to 300°C. It is found that the density of the tail states in the TFT annealed at 300°C (showing the lowest LFN) is prominently lower than those in the TFTs annealed at 250°C and 150°C. The densities of the tail states in the TFTs annealed at 250°C and 150°C (indicating similar LFN) are almost the same. In addition, it is clearly observed that the increased DOS of the a-IGZO TFT subjected to ac gate voltage stress results in a higher LFN compared with one without electrical stress. Hooges parameters αHs are extracted to be ~4.5 × 10-3 (for the TFT annealed at 300°C) and ~1 × 10-2 (for the TFTs annealed at 25°C and 150°C as well as for the TFT annealed at 300°C after the application of electrical ac stress). Therefore, the role of an a-IGZO subgap DOS on a LFN characteristic seems to be originated from the generation-recombination noise-induced carrier number fluctuation (via trap centers in the DOS tail states) while its correlation with the carrier mobility fluctuation is not clear except for the slope close to -1 in the logarithmic curve with the normalized power spectral density versus the gate overdrive voltage.

P‐204L: Late‐News Poster: Subgap Density of States‐Based Amorphous Oxide Thin Film Transistor Simulator (DAOTS) for Process Optimization and Circuit Design

As the oxide TFT-oriented simulator, the subgap density of states- based amorphous oxide TFT simulator (DAOTS) is proposed, implemented, and demonstrated for a-InGaZnO TFTs. It consists of the parameters having their physical meanings. Moreover, concrete techniques for parameter extraction are supplied. Most preferably, the quantitative self-consistency with experimental data is guaranteed in DAOTS.

Comparison of Electrical Properties and Bias Stability of Double-Gate a-HIZO TFTs According to TFT Structure

We fabricated two types of double-gate amorphous hafnium-indium-zinc oxide thin-film transistors: a back-channel etch (BCE) type and an etch stopper (ES) type. The normalized on-current and field-effect mobility of the BCE type are larger than those of the ES type. Furthermore, when applied with a positive bias stress, stability trends compared for each single-gate device are different according to structures. We suggest that the reason for the different electrical properties and bias stability originates from the ES structure in which some regions under the source/drain electrodes block the top-gate field; thus, there is no carrier accumulation or charge trapping into the dielectric layer.

P‐205L: Late‐News Poster: Comparison between a‐InGaZnO and a‐InHfZnO TFTs in Perspective of Subgap Density of States (DOS) in Active Film

The extraction of acceptor-like subgap DOS (gA(E)) in a-InGaZnO and a-InHfZnO TFTs is demonstrated by using multi-frequency C- V technique. The DC performance and negative bias stress (NBS)- induced instability are compared in perspective of gA(E). The superior stability of a-InHfZnO TFT is deduced to be originated from donor-like DOS gD(E).

P-202L: Late-News Poster: Density-of-States Based Analysis on the Effect of Active Thin-film Thickness on Current Stress-induced Instability in Amorphous InGaZnO AMOLED Driver TFTs

The effect of the active layer thickness (TIGZO) on the constant current stress (CCS)-induced threshold voltage shift (ΔVT) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) for AMOLED drivers is investigated by using a subgap density-of-states (DOS) model and simulation. The CCS-induced positive ΔVT in a-IGZO TFT with a thicker TIGZO is larger than that in a-IGZO TFTs with a thinner TIGO. It is originated from more activated charge trapping (60∼80 % in total ΔVT) and DOS creation due to a higher surface electric field with a thicker TIGZO. Our results show that using thinner active layer in a-IGZO TFTs is desirable for high performance and highly stable AMOLEDs if the quality of thin-film bulk is guranteed irrespective of TIGZO.

P-203L: Late-News Poster: Analytical I-V and C-V Models for Amorphous InGaZnO TFTs and Their Application to Circuit Simulations

Analytical current and capacitance models for amorphous Indium-Gallium-Zinc-Oxide Thin film transistors (a-IGZO TFTs) are proposed for application to the simulation of a-IGZO TFT-based circuits. The accuracy of the proposed models are verified by comparing the measured I-V and C-V characteristics with calculated ones and the simulation result of a-IGZO TFT-based circuits. The proposed models are expected to be useful both for the optimization of fabrication process and for the prospective estimation of the effect of process conditions on the circuit performance.