Jai Gopal Pandey

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications

Similarity measures are used in diverse signal-processing applications. Bhattacharyya coefficient is one of the most popular similarity measures that is widely used in many image/video processing applications. Several of these applications need to compute similarity measure between probability density functions of local image statistics. In this paper, an efficient hardware architecture is proposed for accelerating the local similarity measure (LSM) computation using Bhattacharyya coefficient. Direct hardware implementation of Bhattacharyya coefficient requires many compute-intensive hardware resources, which slow down the overall computation process. Data path of the proposed architecture utilizes fixed-point arithmetic and is based on the logarithmic number system. Fast binary logarithmic and antilogarithmic computing units are deployed to realize the required complex arithmetic operations. The histogram computation is accomplished using single-cycle read-modify-write operations on the received image data stored in DDR2 SDRAM. The proposed architecture is realized in the Virtex-5 xc5vfx70t FPGA device of Xilinx ML-507 platform. The device utilization of the implemented architecture shows that it utilizes 4.5% FPGA slices, 5.4% Block RAMs and 27.34% DSP48E slices.

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Otsus global automatic image thresholding technique is widely used in various computer vision-based applications. This paper presents a resource-efficient architecture for the design of Otsus thresholding algorithm and its implementation in field-programmable gate array (FPGA). The proposed architecture is implemented for a 640x480 size of input image that is captured by a real-time high-resolution analog camera and buffered in a DDR2 SDRAM memory. The computation of between-class variance in Otsus algorithm requires the evaluation of a normalized cumulative histogram, mean and cumulative moments, which need single-cycle read-modify-write operations. These operations are achieved by incorporating the FPGAs slices, dual-port Block RAM memories and DSP slices with DDR2 SDRAM as a frame buffer. The data path of the architecture is fixed-point arithmetic based and it does not require any divider. The proposed design is implemented in Xilinx Virtex-5 xc5vfx70tffg1136-1 FPGA device, available on the Xilinx ML-507 platform. In order to develop the required hardware and software in an integrated method, the Xilinx Embedded Development Kit (EDK) design tool is used.

An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation

Lightweight cryptography plays an essential role for emerging authentication-based pervasive computing applications in resource-constrained environments. In this paper, we have proposed resource-efficient and high-performance VLSI architectures for PRESENT block cipher algorithm for the two key lengths 80-bit and 128-bit, namely PRESET-80 and PRESENT-128. The FPGA implementations of these architectures have been done on LUT-6 technology based Xilinx Virtex-5 XC5VFX70T-1-FF1136 FPGA device. These architectures have a latency of 33 clock cycles, run at a maximum clock frequency of 306.84 MHz and provide throughput of 595.08 Mbps. They have been compared with the two different established architectures. It has been observed that the PRESENT-80 architecture consumes 20.3% lesser FPGA slices and there is a gain of 25.4% in throughput. Similarly, the PRESENT-128 architecture requires 20.7% lesser FPGA slices alongwith a reduction in the latency by 27.7% and an overall increase of throughput by 69.1%.

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure

Mean shift procedure can be used in many image/video processing applications for efficiently solving problem of accurate object localization by the computation of center of gravity (CoG) measure. Real-time object localization is a compute-intensive and time-consuming task that is difficult to perform by using only software-based approach. Thus, invariably there is a requirement of accelerating hardware solutions with special emphasis towards efficient and high-performance architectures. This paper presents an embedded framework alongwith required hardware architectures for accurate target localization using CoG computation in the context of object tracking application. Xilinx ML-507 platform has been used to provide a field-programmable gate array (FPGA) implementation of all the required building blocks. The design uses some of the standard intellectual property (IP) elements and an embedded PowerPC processor available in Virtex-5 FX FPGA device of the platform. A high-resolution camera is utilized to capture 640×480 resolution real-time video frames, which are buffered in a DDR2 SDRAM memory of the platform. To compute complex arithmetic operations, the proposed architectures utilize binary logarithm and antilogarithm units with fixed-point datapath. FPGA device utilization shows that the proposed architectures use small number of FPGA slices and a few off-the-shelf FPGA macro elements.

Architectures and algorithms for image and video processing using FPGA-based platform

The work illustrates the use of platform-based design to achieve efficiently-configured hardware-software system solution that can meet the conflicting demands of high performance, low power and quick turnaround time for embedded system development. It presents embedded system design techniques using field-programmable gate arrays (FPGAs) for image and video processing application. Here, by identifying, building and integrating all necessary hardware and software components, an embedded implementation of a kernel-based mean shift (KBMS) object tracking algorithm has been proposed [1]. To fulfill the specific needs of hardware/software implementation Virtex-5 FXT FPGA device (which has an embedded PowerPC processor) available on Xilinx ML-507 platform has been used [2].