Jai-Hoon Sim

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

Elimination of parasitic bipolar-induced breakdown effects in ultra-thin SOI MOSFETs using narrow-bandgap-source (NBS) structure

In this paper, we introduce the Si-SiGe narrow bandgap-source (NBS) SOI device structure in order to improve the low drain-to-source breakdown voltage (V/sub BD/) in ultra-thin SOI devices. Reducing the potential barrier of valence band between source and body by applying the SiGe layer at the source region, we can improve the drain-to-source breakdown voltage by suppressing the hole accumulation in the body. As confirmed by 2D simulation results, NBS-SOI devices provide excellent performance compared to conventional SOI devices. >

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

An analytical deep submicron MOS device model considering velocity overshoot behavior using energy balance equation

In order to evaluate the velocity overshoot phenomenon in the deep submicron MOS devices, the energy balance equation should be incorporated with the drift-diffusion equation that includes thermoelectric diffusion. This paper presents an analytical current model for deep submicron MOS devices by solving the energy balance equation. Our model results show good agreement with experimental results. We have successfully derived the drain current model composed of drift and thermoelectric currents. >

Low voltage high speed circuit designs for giga-bit DRAMs

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.

High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's

In this paper, the cell transistor design issues for the Gbit level DRAMs with the isolation pitch of less than 0.2 /spl mu/m caused by the inverse-narrow-channel effect (INCE) and the neighboring storage-node E-field penetration effect (NSPE) will be discussed. Then we propose novel DRAM cell transistor structure by employing metallic shield inside the shallow trench isolation (STI). As confirmed by three-dimensional (3-D) device simulation results, by suppressing the inverse narrow-channel effect and the neighboring storage-node E-field penetration effect using metallic shield inside STI, we can obtain reliable cell transistors with low-doped substrate, low junction leakage current and uniform V/sub TH/ a distribution regardless of the active width variation.

Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology

We present CMOS transistors with n/sup +//p/sup +/ source/drain extensions doped by AsH/sub 3/ and BF/sub 3/ plasma immersion ion implantation (PIII) for the first time. We successfully demonstrate n/sup +//p/sup +/ shallow junctions with R/sub s/<1 k/spl Omega//sq for CMOS devices. No degradation in gate oxide integrity is observed for either AsH/sub 3/ or BF/sub 3/ PIII. Compared to conventional ion implantation, PIII provides much better short-channel effects and approximately 50% I/sub off/ reduction for both nMOS and pMOS devices. In particular, the flat threshold voltage roll-off and good performance in buried-channel pMOS devices is the best-reported PIII data to date.

The impact of isolation pitch scaling on V/sub TH/ fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration

This paper presents the accelerated inverse narrow channel effect of DRAM cell transistors caused by lateral E-field penetration from drain/source junctions of neighboring cell transistors. This phenomenon strongly increases the threshold voltage fluctuation of cell transistors depending on the junction biases of neighboring cell transistors and will impose physical size and the voltage scaling constraints for the Gigabit level DRAM technology.

An energy balance equation based 0.1 /spl mu/m MOSFET model including velocity overshoot behavior

In order to evaluate the velocity overshoot phenomenon in the deep submicron MOS devices, the energy balance equation should be incorporated with the drift-diffusion equation that includes thermoelectric diffusion. This paper presents an analytical current model for deep submicron MOS devices by solving the energy balance equation. Our model results show good agreement with experimental results. We have successfully derived the drain current model composed of drift and thermoelectric currents.