Jaideep Chandran

Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter

A reconfigurable digital root raised cosine (RRC) filter for a UMTS terrestrial radio access (UTRA) mobile terminal receiver is implemented on a Xilinx Vitrex II Pro Field Programmable Gate Array (FPGA). The filter employs a finite impulse response (FIR) and monitors in-band and out-of-band received signal powers and calculates the appropriate filter length that meets the bit-energy to interference ratio (Eb/No) of the system. The results presented are for the time division duplex (TDD) mode of UTRA.

A Review of Blood Gas Sensors and a Proposed Portable Solution

Blood gasses are one of the vital signs monitored by medical practitioners for critically ill patients and as preventive health care measures for potential heart disease patients. Measurement of blood gasses in a quick, effective way, without compromising on accuracy is one of the fundamental topics for research today and is in tune with the demands of the medical fraternity. The objective of this paper is to review the theory of blood gas measurement and the current technological solutions used to measure blood gasses non-invasively and continuously. This paper finally presents proposed research that will foresee portable, noninvasive blood gas monitoring solutions.

Implementation of a colorimetric algorithm for portable blood gas analysis

This paper presents the implementation results of a colorimetric algorithm for portable blood gas analysis. The need for diagnostic data to be available from the patients living environment has given rise to the need for portable diagnostic equipment. Blood gas analysis is an important diagnostic tool which provides the medical practitioner with insights in to the health of the respiratory system and kidneys. Present day analysers are big, bulky, and expensive and run on mains supply. The paper discusses the implementation of an algorithm based on the change of colour of an indicator with respect to the change in pH. The algorithm maps the change in colour to a mathematical equation. The equation is implemented using floating point arithmetic architectures. The paper presents the implementation of the algorithm using the Altera Stratix FPGA and 0.35µm CMOS process. The design is aimed low power consumption and size. The design met the timing constraints for an operating speed of 50 MHz and consumes 2.78W of power.