Jaidev P. Patwardhan

A large, fast instruction window for tolerating cache misses

Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism.This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a long latency operation (e.g., cache miss) cannot execute until that source operation completes. These instructions are moved out of the conventional, small, issue queue to a much larger waiting instruction buffer (WIB). When the long latency operation completes, the instructions are reinserted into the issue queue. In this paper, we focus specifically on load cache misses and their dependent instructions. Simulations reveal that, for an 8-way processor, a 2K-entry WIB with a 32-entry issue queue can achieve speedups of 20%, 84%, and 50% over a conventional 32-entry issue queue for a subset of the SPEC CINT2000, SPEC CFP2000, and Olden benchmarks, respectively.

Design tools for a DNA-guided self-assembling carbon nanotube technology

The shift in technology away from silicon complementary metal–oxide semiconductors (CMOS) to novel nanoscale technologies requires new design tools. In this paper, we explore one particular nanotechnology: carbon nanotube transistors that are self-assembled into circuits by using DNA. We develop design tools and demonstrate how to use them to develop circuitry based on this nanotechnology. (Some figures in this article are in colour only in the electronic version)

NANA: A nano-scale active network architecture

This article explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are (1) limited node size, (2) random node interconnection, and (3) high defect rates. We present and evaluate an accumulator-based active network architecture that is compatible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly.

A defect tolerant self-organizing nanoscale SIMD architecture

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. Bottom-up manufacturing techniques, like self assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities.This paper explores a defect tolerant SIMD architecture. A key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system (~1cm2 area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems (>1cm2), the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.

Communication breakdown: analyzing CPU usage in commercial Web workloads

There is increasing concern among developers that future Web servers running commercial workloads may be limited by network processing overhead in the CPU as 10Gb Ethernet becomes prevalent. We analyze CPU usage of real hardware running popular commercial workloads, with an emphasis on identifying networking overhead. Contrary to much popular belief, our experiments show that network processing is unlikely to be a problem for workloads that perform significant data processing. For the dynamic Web serving workloads we examine, networking overhead is negligible (3% or less), and data processing limits performance. However, for Web servers that serve static content, networking processing can significantly impact performance (up to 25% of CPU cycles). With an analytical model, we calculate the maximum possible improvement in throughput due to protocol offload to be 50% for the static Web workloads.

A self-organizing defect tolerant SIMD architecture

The continual decrease in transistor size (through either scaled CMOS or emerging nanotechnologies) promises to usher in an era of tera to peta-scale integration but with increasing defects. Regardless of fabrication methodology (top-down or bottom-up), defect-tolerant architectures are necessary to exploit the full potential of future increased device densities. This article explores a defect-tolerant SIMD architecture (SOSA) that self-organizes a large number of limited capability nodes with high defect rates into SIMD processing elements. Simulation results show that SOSA matches or exceeds the performance of conventional systems for moderate to large problems, but with lower power density.

Self-Assembled Networks: Control vs. Complexity

DNA-based self-assembly of nanoelectronic devices is an emerging technology that has the potential to enable tera-to peta-scale device integration. However, self-assembly currently is limited to manufacturing small computing blocks (nodes) which must then be interconnected to build a larger computing system. In this paper, the authors study node networks created by varying control over three aspects of the self-assembly process (node placement, node orientation, and inter-node link creation). In particular, the authors examine the tradeoff between node complexity and control required during self-assembly to maximize the number of connected nodes in the network. As the level of control decreases, the authors find that node communication hardware needs to be augmented to allow link sharing between several transceivers. This also results in better network connectivity in the presence of defective nodes and links. Finally, the authors show that for a data parallel architecture with enough available nodes, the specific network topology has a negligible effect on performance

Exploring the benefits of a continuous consistency model for wireless Web portals

Wireless devices currently provide real time access to personalized information such as headlines, email, stock quotes, and online auctions. Retrieving all updates to such rapidly changing information is wasteful of both network bandwidth and battery power. Existing consistency models for such services allow for only coarse grained timeouts on how often information should be retrieved. The authors argue for the benefits of a continuous consistency model for user access to Internet portal services. Using this model, users are able to specify the maximum error in their view of the data. For instance, users may specify that they wish to receive an updated stock quote only if the users view diverges from the actual value by more than 3%. Services may also use application-specific semantics to control data consistency, e.g., new bids carry more weight as the auction draws to a close. We use a simulator to model the bandwidth and energy benefits available from a more flexible consistency model. Such benefits depend upon the rate at which underlying data values change. To capture representative distributions, we use a trace based study of updates to weather, news, and stock quotes from a popular portal to determine representative distribution ranges. Our initial results indicate bandwidth and energy savings that increase as users are willing to tolerate larger bounds on data accuracy.