Jameel Ahmed

A novel image encryption based on Lorenz equation, Gingerbreadman chaotic map and S 8 permutation

Internet is used as the main source of communication throughout the world. However due to public nature of internet data are always exposed to different types of attacks. To address this issue many researchers are working in this area and proposing data encryption techniques. Recently a new substitution box has been proposed for image encryption using many interesting properties like gingerbread-man chaotic map and S8 permutation. But there are certain weaknesses in aforesaid technique which does not provide sufficient security. To resolve the security issue an enhanced version of existing technique is proposed in this paper. Lorenz chaotic map based confusion and diffusion processes in existing technique are employed. Lorenz map is used to remove strong correlation among the plain text image pixels. In diffusion stage a random matrix is generated through lorenz chaotic map and XORed with shuffled image. It the end, existing gingerbread-man chaotic map based S-box is applied to extract the final cipher text image. The proposed enhanced scheme is analysed by statistical analysis, key space analysis, information entropy analysis and differential analysis. In order to ensure the robustness and higher security of proposed scheme, results via Number of Pixel Rate Change (NPRC)and Unified Average Change Intensity (UACI) tests are also validated. 9

An image encryption technique based on coupled map lattice and one-time S-Boxes based on complex chaotic system

An efficient image encryption technique based on one-time nonlinear component for block cipher is presented in this paper. Three S-Boxes are generated by complex chaotic system, whose initial values are dependent on both the random noise and the plain image. Each S-box randomly takes turns to encrypt one of the color components in each pixel adhering to the switching sequence, which is also generated by the complex chaotic system. Subsequently, the two-stage diffusion to process images is applied. The cipher image is expanded into two composed of selected four bit-planes and diffuse them at bit-level as first stage diffusion, then reconstruct them as the input of block diffusion, which is served as second stage diffusion. The chaotic coupled map lattice employed in this method generate pseudo-random sequences in block diffusion phase. The experiment results and analysis have proved the novel image encryption method is practical and effective for encryption applications.

RFID-WSN Integrated Architecture for Energy and Delay- Aware Routing

The book identifies the performance challenges concerning Wireless Sensor Networks (WSN) and Radio Frequency Identification (RFID) and analyzes their impact on the performance of routing protocols. It presents a thorough literature survey to identify the issues affecting routing protocol performance, as well as a mathematical model for calculating the end-to-end delays of the routing protocol ACQUIRE; a comparison of two routing protocols (ACQUIRE and DIRECTED DIFFUSION) is also provided for evaluation purposes. On the basis of the results and literature review, recommendations are made for better selection of protocols regarding the nature of the respective application and related challenges. In addition, this book covers a proposed simulator that integrates both RFID and WSN technologies. Therefore, the manuscript is divided in two major parts: an integrated architecture of smart nodes, and a power-optimized protocol for query and information interchange.

Challenges and Issues in the WSN and RFID

In this chapter research based work encompassing present and future trends of RFID and WSN has been presented. Various research aspects in the area of security with respect to sensing network and identification have substantially been explored and pointed out for future investigation. Efforts have been made to incorporate the latest and updated research so as to provide the premises for the work that has been done in the subject area.

Optimizing energy and throughput for MPSoCs: an integer particle swarm optimization approach

Most of recent research in multicore processor architectures has been shifted towards reconfigurable architectures due to increasing complexity of computing systems. These systems provide better application-specific energy and throughput balance with their reconfigurable behavior. They perform automatic run time resource allocation for an application as per its needs. But in terms of performance, current methodologies produce some unpredictable results because of the actual variety of the workloads. Therefore, we need optimization of the system resources usage by employing some optimization algorithms. Early research in the field of reconfigurable architecture using optimization algorithms has produced efficient results for energy consumption with the reconfiguration of cache sizes and associativity, number of cores and operating frequency. In this research, we propose particle swarm optimization (PSO) based algorithm, Integer PSO (IPSO) for design space exploration of reconfigurable computer architectures to have better energy and throughput balance. The results obtained by IPSO are evaluated by using various SPLASH-2 benchmark applications. Evaluation shows notable reduction in energy consumption without major effect on throughput. Simulation results also support the use of IPSO in design space exploration of multicore reconfigurable processor architectures.

NSGA-II-Based Design Space Exploration for Energy and Throughput Aware Multicore Architectures

ABSTRACT Multicore architectures are mainstream due to ever increasing demand of throughput by modern applications. However, the suboptimal utilization of available resources in these architectures may imply an inevitable energy overhead. This energy overhead can only be avoided if the multicore systems support reconfiguration of available resources as per application demand. To achieve the target objectives (i.e., Energy efficiency with Throughput maximization) in multicore systems, many decision variables need to be optimized or analyzed to find the better trade-off. Heuristic-based approaches are aimed to provide a good-enough solution instead of a lengthy exhaustive search. This paper presents an Evolutionary Algorithm (EA)-based approach, i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II). Three decision variables, i.e., number of cores, cache size and frequency are used to find best solution. The proposed approach is validated over a set of parallel benchmarks using a cycle accurate simulator. The results show a significant amount of energy saving along with minimal impact on the throughput of the system.

XenoJetBench: An open source hard-real-time multiprocessor benchmark

Standard benchmark tools play an integral part in the design process for performance evaluation of a computer system. A previously proposed tool, JetBench, is an Open Source multiprocessor benchmark that can be used to analyze the performance of a specific target platform. JetBench uses reaction-propulsion engine parameters and thermodynamical equations used in the NASAs EngineSim program, and emulates reaction-propulsion engine performance calculator. This application is platform independent, i.e., target specific libraries, hardware counters and timers are not required. This paper presents an updated and enhanced version of JetBench named as ‘XenoJetBench’. XenoJetBench is aimed to provide hard-real-time (HRT) performance evaluation of jet engines thermodynamic parameters through the integration of a HRT framework on a real-time operating systems kernel; hence reducing the number of missed deadlines. In addition to that XenoJetBench is programmed to provide priority based thread scheduling of thermodynamic calculations. The results show that XenoJetBench gives no missed deadline for single and dual core processors and maximum number of missed deadlines are reduced to 9 for 16 cores.

Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications

The trade-off between performance and power consumptionfor dynamic and complex applications is inevitable andis considered as a key design challenge for system architects. Performance statistics for hard real time systems must be readilyavailable for a feedback system, specifically for reconfigurablearchitectures. The feedback in terms of performance statisticscan be useful for run-time reconfiguration of a system drivenby various optimization algorithms. A systems performancecan be monitored at run-time using hardware performancecounters (HPCs) aiming to improve performance with minimaloverheads in terms of energy, cost and complexity. Therefore, this paper presents an enhanced version of LEON3 architecturewhich includes support for the performance monitoring scheme(PMS) to analyze dynamic events such as cache hit/miss ratioand the number of cycles consumed by running applications. This modification can be useful as performance evaluation isconsidered as a key metric in real-time reconfigurable systems. The significance of PMS is highlighted by various power relatedmathematical models to build throughput and energy awareembedded systems. This enhanced SoC has been tested withvarious standard benchmarks such as Dhrystone, Coremark, Stanford suite and MiBench suite. All the results have been testedwith simulator and with real hardware on Xilinx ML509 FPGAprototyping board. The result shows the error percentage of lessthan 7 when compared with TSIM. This enhancement can beuseful for real time space applications with a minimal hardwareoverhead of about 1-3% LUTS and 10.8% in case of Block RAMs.

Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System

This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.