James A. Culp

Compensating non-optical effects using electrically driven optical proximity correction

Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature. Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA) variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC can be leveraged to compensate circuit performance for matching designer intent. Compared to existing compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage variability, which potentially translates to mitigation of circuit-limited yield.

Electrically driven optical proximity correction

Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

Reducing DfM to practice: the lithography manufacturability assessor

The need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. Three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. The importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. The need for extensive experimental calibration and improved simulation accuracy is also highlighted.

Process window OPC for reduced process variability and enhanced yield

As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Analysis of systematic variation and impact on circuit performance

Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub- 65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no existing design methodology to study the variational (across process window) impact of all these effects simultaneously. In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout dependent effects on circuit performance. We describe physical design models used to describe four major sources of parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then develop a methodology to determine variability in circuit performance based on integrating the above device models with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We believe a flow that is capable of understanding process-induced parametric variability will have major advantages in terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and advantages in terms of diagnosis and silicon debug.

Coupling timing objectives with optical proximity correction for improved timing yield

Design-manufacturing co-optimization has been earmarked as a key enabler of future technology scaling. Current manufacturing methods treat all transistors equally irrespective of their criticality in the design flow. In the presence of variations in the lithographic process, this leads to timing violations which reduces chip yield. In this paper, we develop a timing-driven process window optical proximity correction (TD-PWOPC) algorithm that tunes the mask generation for each transistor based on its electrical criticality in the design. Our method utilizes knowledge of timing information to generate delay bounds on each cell. It then develops a process variation aware OPC cost function for each cell to ensure that post-lithography delay lies within these bounds. This method uses a single image simulation coupled with simplified models for regular polysilicon layouts to predict though-process performance. We finally use a gradient-descent algorithm to minimize this cost function. Results show that the use of TD-PWOPC can reduce delay errors significantly compared to regular OPC at small runtime overheads of 4.5%.

Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM)

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

Practical DTCO through design/patterning exploration

Design Technology Co-Optimization (DTCO) becomes more important with every new technology node. Complex patterning issues can no longer wait to be detected experimentally using test sites because of compressed technology development schedules. Simulation must be used to discover complex interactions between an iteration of the design rules, and a simultaneous iteration of an intended patterning technology. The problem is often further complicated by an incomplete definition of the patterning space. The DTCO process must be efficient and thoroughly interrogate the legal design space for a technology to be successful. In this paper we present our view of DTCO, called Design and Patterning Exploration. Three emphasis areas are identified and explained with examples: Technology Definition, Technology Learning, and Technology Refinement. The Design and Patterning Exploration flows are applied to a logic 1.3x metal routing layer. Using these flows, yield limiting patterns are identified faster using random layout generation, and can be ruled out or tracked using a database of problem patterns. At the same time, a pattern no longer in the set of rules should not be considered during OPC tuning. The OPC recipe may then be adjusted for better performance on the legal set of pattern constructs. The entire system is dynamic, and users must be able to access related teams output for faster more accurate understanding of design and patterning interactions. In the discussed example, the design rules and OPC recipe are tuned at the same time, leading to faster design rule revisions, as well as improved patterning through more customized OPC and RET.

High-Value Design Techniques for Mitigating Random Defect Sensitivities

Todays sophisticated design-for-manufacturability (DFM) methodologies provide a designer with an overwhelming amount of choices, many with significant costs and unclear value. The technology challenges of subwavelength lithography, new materials, device types/sizes, etc., can mask the underlying random defect yield contribution which ultimately dominates mature manufacturing, and the distinction between technology limitations and process excursions must also be understood. The best DFM strategy fully exploits all of the available techniques that mitigate a designs sensitivity to random defects where the value is clearly quantifiable, yet few designers seize this opportunity. This paper provides a roadmap through the entire design flow and gives an overview of the various options.