James A. Rowson

Interface-based design

A new system design methodology is proposed that separates communicationfrom behavior. To demonstrate the methodology weapplied it to a simple ATM design. Since verification is clearly amajor stumbling block for large system design, we focussed on theverification aspects of our methodology.In particular, a simulator was developed that is based on the communicationparadigm typical of our methodology. The simulatorgives substantial performance improvements without sacrificinguser access to detail.Finally, the potential for this methodology to improve verification,modeling and synthesis is explored.

Hardware/Software Co-Simulation

Hardware-software co-simulation refers to verifying that hardware and software function correctly together. This has traditionally been a task performed after the prototype hardware is available using in-circuit emulators and other techniques. With hardware-software co-design and embedded processors within large single ICs, it is more necessary to verify correct functionality before the hardware is built. This paper surveys the techniques available for co-simulation with an eye toward the strengths and weaknesses of each.

Automatic synthesis of interfaces between incompatible protocols

At the system level, reusable Intellectual Property (or IP) blocks can be represented abstractly as blocks that exchange messages. The concrete implementations of these IP blocks must exchange the messages through complex signaling protocols. Interfacing between IP that use different signaling protocols is a tedious and error prone design task. We propose using regular expression based protocol descriptions to show how to map the message onto a signaling protocol. Given two protocols, an algorithm is proposed to build an interface machine. We have implemented our algorithm in a program named PIG that synthesizes a Verilog implementation based on a regular expression protocol description.

Generation of software tools from processor descriptions for hardware/software codesign

An experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed.

ICARUS: An Interactive Integrated Circuit Layout Program

ICARUS (Integrated Circuit ARtwork Utility System) is a software system which allows the user to create and modify an integrated circuit layout directly on a refresh CRT screen. The system can generate check plots on the matrix type printers available from Versatec or on a raster-scan laser printer such as the 9700 Xerox has recently announced. The ICARUS files can be used to create standard pattern generation tapes from which integrated circuit masks can be made. All the software to accomplish these various steps runs on a small experimental minicomputer known as the Alto.

RIOT -- A Simple Graphical Chip Assembly Tool

Riot is a simple interactive graphical tool designed to facilitate the assembly of cells into integrated systems. Riot supplies the user with primitive operations of connection -- abutment, routing and stretching -- in an interactive graphic environment. The designer retains full control of the design, including the assignment of positions to instances of cells and the choice of connection mechanism. The computer takes care of the tedious and exacting implementation detail, guaranteeing that connections are made correctly. The powerful connection primitives give the user of Riot the ability to quickly assemble a custom chip from a collection of low-level cells. This document provides a discussion of the motivation for Riot and a description of the Riot chip assembly system, its capabilities and its use.