James A. Slinkman

Two-dimensional surface dopant profiling in silicon using scanning Kelvin probe microscopy

A simultaneous combination of scanning Kelvin probe microscopy and scanning atomic force microscopy has been applied to the problem of profiling dopant concentrations in two dimensions in silicon microstructures. By measuring the electrochemical potential difference which minimizes the electrostatic force between probe tip and sample surface, the work‐function difference between the tip and surface is estimated. To the extent that this work‐function difference is a consequence of the dopant concentration at or near the sample surface, doping profiles are inferred from the measurement. Structures examined and presented here include contact holes, and the technologically significant lightly doped drain of a metal–oxide–silicon field‐effect transistor. Using this methodology, one can distinguish relative changes in dopant concentration with lateral resolution less than 100 nm. Sample preparation is minimal, and measurement time is fast compared to other techniques. The measurements have been compared to pred...

Lateral dopant profiling with 200 nm resolution by scanning capacitance microscopy

Measurement of dopant density in silicon with lateral resolution on the 200 nm scale has been demonstrated with a near‐field capacitance technique. The technique is based upon the measurement of local capacitance between a 100 nm tip and a semiconducting surface. Lateral dopant imaging is achieved by the measurement of the voltage‐dependent capacitance between tip and sample due to the depletion of carriers in the semiconductor, as the tip is scanned laterally over the surface. Measurements of dopant density have been demonstrated over a dopant range of 1015–1020 cm−3. Capacitance‐voltage measurements have been made on a submicrometer scale.

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

Capacitive effects on quantitative dopant profiling with scanned electrostatic force microscopes

A force‐based scanning Kelvin probe microscope has been applied to the problem of dopant profiling in silicon. Initial data analysis assumed the detected electrostatic force couples the sample and only the tip at the end of a force sensing cantilever. Attempts to compare measurements quantitatively against device structures with this simple model failed. A significant contribution arises from the electrostatic force between the sample and the entire cantilever, which depends strongly upon the relative size of the tip, cantilever, and lateral inhomogeneities in the surface topography and material composition of the sample. Actual and simulated measurements which demonstrate the characteristic signature of this effect are presented.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors☆

Abstract A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, and ESD test data, will be shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Imaging integrated circuit dopant profiles with the force‐based scanning Kelvin probe microscope

A force‐based scanning Kelvin probe microscope has been used to image dopant profiles in silicon for integrated circuit devices on a submicron scale. By measuring the potential difference which minimizes the electrostatic force between a probe and surface of a sample, an estimate of the work function difference between the probe and surface may be made. To the extent that this work function difference is a consequence of the dopant concentration near the sample surface, doping profiles are inferred from the measurements. An overview of the measurement technique is presented, along with several examples of resulting dopant imaging of integrated circuits.

Shallow trench isolation double-diobe electrostatic discharge circuit and interaction with DRAM output circuitry

Abstract Electrostatic discharge (ESD) performance of a shallow-trench-isolation double-diode protection circuit in CMOS technology is discussed. This paper highlights the sensitivities of these devices to semiconductor process parameters, interaction with chip circuitry and advanced failure analysis techniques.

Lateral dopant profiling on a 100 nm scale by scanning capacitance microscopy

Measurement of dopant density in silicon with lateral resolution on the 100 nm scale has been demonstrated with a ‘‘near field’’ capacitance microscope. The technique is based upon the measurement of local capacitance between a 100 nm tip and the sample surface as the tip is scanned over the surface. The capacitive microscope used to image the dopant is capable of measuring capacitance variations of 3×10−22 F/(Hz)1/2, and previously has demonstrated a 25 nm resolution on metallic surfaces. Dopant imaging is achieved by scanning the tip under feedback control close to a silicon surface, and measuring the capacitance variations. Several types of measurements have been made on the submicrometer scale. First, direct two‐dimensional visualization of the dopant in silicon has been achieved by this nondestructive, noncontacting technique. Second, capacitance versus voltage (C–V) measurements have been made with high spatial resolution, providing the means for the measurement of many of the properties of silicon ...

Efficient Quantum Correction Model for Multi-dimensional CMOS Simulations

We present a new Quantum correction algorithm suitable for multi-dimensional CMOS simulations. The quantum effects are included using the Modified Local Density Approximation (MLDA). Physically accurate spatial distribution of quantized carriers can be predicted with only ten to twenty percents increased of computation time. The algorithm is also suitable to integrate into a device simulator. Simulation results are in good agreement with experimental data.