James B. Hannon

Large-Area Graphene Single Crystals Grown by Low-Pressure Chemical Vapor Deposition of Methane on Copper

Graphene single crystals with dimensions of up to 0.5 mm on a side were grown by low-pressure chemical vapor deposition in copper-foil enclosures using methane as a precursor. Low-energy electron microscopy analysis showed that the large graphene domains had a single crystallographic orientation, with an occasional domain having two orientations. Raman spectroscopy revealed the graphene single crystals to be uniform monolayers with a low D-band intensity. The electron mobility of graphene films extracted from field-effect transistor measurements was found to be higher than 4000 cm(2) V(-1) s(-1) at room temperature.

The influence of the surface migration of gold on the growth of silicon nanowires

Interest in nanowires continues to grow, fuelled in part by applications in nanotechnology. The ability to engineer nanowire properties makes them especially promising in nanoelectronics. Most silicon nanowires are grown using the vapour–liquid–solid (VLS) mechanism, in which the nanowire grows from a gold/silicon catalyst droplet during silicon chemical vapour deposition. Despite over 40 years of study, many aspects of VLS growth are not well understood. For example, in the conventional picture the catalyst droplet does not change during growth, and the nanowire sidewalls consist of clean silicon facets. Here we demonstrate that these assumptions are false for silicon nanowires grown on Si(111) under conditions where all of the experimental parameters (surface structure, gas cleanliness, and background contaminants) are carefully controlled. We show that gold diffusion during growth determines the length, shape, and sidewall properties of the nanowires. Gold from the catalyst droplets wets the nanowire sidewalls, eventually consuming the droplets and terminating VLS growth. Gold diffusion from the smaller droplets to the larger ones (Ostwald ripening) leads to nanowire diameters that change during growth. These results show that the silicon nanowire growth is fundamentally limited by gold diffusion: smooth, arbitrarily long nanowires cannot be grown without eliminating gold migration.

Toward High-Performance Digital Logic Technology with Carbon Nanotubes

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moores law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Layer-Resolved Graphene Transfer via Engineered Strain Layers

Monolayer Graphene via Two Transfers Oriented monolayers of graphene containing some bilayer regions can be formed on silicon carbide crystal surfaces, but, to be cost effective, the graphene needs to be exfoliated and transferred to other substrates so that the silicon carbide crystal can be reused. Kim et al. (p. 833, published online 31 October) used a nickel film grown to a thickness designed to impart a particular surface stress as a “handle” to exfoliate the graphene layer for transfer to a silica substrate. An additional gold layer was then used to remove the excess monolayer from the bilayer regions to create a monolayer suitable for electronics applications. A two-step exfoliation process allows multiple transfers of oriented monolayer graphene from a silicon carbide surface. The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

Selective placement of carbon nanotubes on oxide surfaces

We describe a method to selectively position carbon nanotubes on Al2O3 and HfO2 surfaces. The method exploits the selective binding of alkylphosphonic acids to oxide surfaces with large isoelectric points (i.e. basic rather than acidic surfaces). We have patterned oxide surfaces with acids using both microcontact printing and conventional lithography. With proper choice of the functional end group (e.g., -CH3 or -NH2), nanotube adhesion to the surface can be either prevented or enhanced.

Directed Assembly of Single-Walled Carbon Nanotubes via Drop-Casting onto a UV-Patterned Photosensitive Monolayer

We report the use of a novel UV-sensitive self-assembled monolayer to selectively deposit single-walled carbon nanotubes from solution using heterogeneous surface wettability. This process combines ubiquitous photopatterning techniques with simple solution processing to yield highly selective and densely packed carbon nanotube patterns. The essential concept behind this process is the change in surface chemistry caused by the UV-induced monolayer reaction. Selective deposition of carbon nanotubes was achieved by drop-casting, and the resulting films show local ordering, indicating that further development of this process will lead to simple technique for large-scale integration.

Spatially-Resolved Structure and Electronic Properties of Graphene on Polycrystalline Ni

We have used in situ low-energy electron microscopy (LEEM) to correlate the atomic and electronic structure of graphene films on polycrystalline Ni with nm-scale spatial resolution. Spatially resolved electron scattering measurements show that graphene monolayers formed by carbon segregation do not support the π-plasmon of graphene, indicating strong covalent bonding to the Ni. Graphene bilayers have the Bernal stacking characteristic of graphite and show the expected plasmon loss at 6.5 eV. The experimental results, in agreement with first-principles calculations, show that the π-band structure of free-standing graphene appears only in films with a thickness of at least two layers and demonstrate the sensitivity of the plasmon loss to the electronic structure.

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.

Argon Assisted Growth of Epitaxial Graphene on Cu(111)

The growth of graphene by catalytic decomposition of ethylene on Cu(111) in an ultra-high vacuum system was investigated with low energy electron diraction, low energy electron microscopy, and atomic force microscopy. Attempts to form a graphene overlayer using ethylene at pressures as high as 10 mTorr and substrate temperatures as high as 900 C resulted in almost no graphene growth. By using an argon overpressure, the growth of epitaxial graphene on Cu(111) is achieved. The suppression of graphene growth without the use of an argon overpressure is attributed to Cu sublimation at elevated temperatures. During the initial stages of growth, a random distribution of rounded graphene islands is observed. The predominant rotational orientation of the islands is within 1 of the Cu(111) substrate lattice.

Ultrathin

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.