James David Strom

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

A 180-ps, 220 K-circuit Bicmos Asic Logic Chip

A 12.7-mm BiCMOS ASIC logic chip with 0.5-pm devices and four levels of metal has a,n extensive I/O and internal circuit library and RAM miscro compilers. CMOS, BiNMOS, and BiCMOS circuit!; are available for optimization of either density or performance, and a chip timing scheme supports intermixing of the circuit types. A wired density of 220K-circuits is achieved. The chip features a central clock receiver and low resistance on the I/O lines.