James G. Mitchell

Aligning chips face-to-face for dense capacitive communication

Conductive electrical interconnections and on-chip transceivers have long been used to provide reliable interconnections between VLSI electronic components, and have dominated the interconnect hierarchy for reasons of manufacturing cost, system packaging, and ease-of-use. VLSI linewidths and on-chip clock speeds have continued to scale, putting pressures on the ability of traditional wires to achieve the offchip bandwidths necessary to fully and efficiently utilize the resources available onchip. When designing chip input and output circuits that communicate conductively, electronic circuit and system designers must design with the constraints of VLSI packages and circuit boards by using advanced circuit techniques such as predistortion, equalization, multilevel coding, and digitally controlled feed-forward clock and data recover blocks commonly referred to as serializer-deserializer (SerDes) transceivers. However, this generally increases the area and power consumption and limits the maximum number of I/O circuits per chip. Current best-in-class Serdes transceivers are expected to yield signaling densities between 1-5 terabits per second per square centimeter (Tbps/cm2) [1].

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Proximity Communication (PxC) facilitates the integration of VLSI chips in a package using near-field capacitive coupling between chips, eliminating the need for solder or wires for I/O at the chip-to-chip interface. PxC provides chip-to-chip interconnect with bandwidth density and energy per bit similar to on-chip I/O, enabling system on a chip performance within a package. We have built early packages to explore assembly concepts and developed test methods for verification of the PxC design space. This package started with an adhesively-bonded three-chip subassembly of two Island chips and one Bridge chip. The two outer Island chips were reflowed to an alumina ceramic substrate. In the resulting package, communication between chips was achieved using PxC from Island to Bridge and then from the Bridge to the other Island. We demonstrated the ability to detect the X, Y, and Z chip-to-chip relative location and the ability to steer PxC data to optimize signal integrity within the package. This paper describes the first demonstration of active monitoring of chip-to-chip alignment during thermal cycling, in a PxC-enabled package. Leveraging this work, future packages will better exploit PxC benefits such as free-space electrical interconnect and re-workability of multi-chip modules.