James Halvis
Westinghouse Electric
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by James Halvis.
Proceedings of SPIE | 1996
Richard Mckee; Donald Lampe; James Halvis; Timothy Henricks; Thomas E. Wilson; William E. Kleinhans; Krishna Linga; Michael J. Lange
Performance of a SWIR FPA targeting LANDSAT S/N levels in the near room temperature (> 220 K) is presented. The FPA consists of a 96 X 25 element InGaAs array with 48 (mu) X 48 (mu) photo-voltaic pixels bump-bonded to a Si multiplexer. Cutoff wavelength of an array is tailored from 1.68 (mu) to 2.4 (mu) . The longer cutoff is required for Band 7. The multiplexer design incorporates a CMOS CCD process and is a 96 channel X 25 TDI scanning array with pixel pitch of 48 (mu) cross track by 96 (mu) intrack. Each unit cell uses a Capacitive Trans-Impedance Amplifier) with Correlated Double Sampling. Other notable chip features include electrically selectable TDI modes (0, 1, 8, 16, and 25), forward and reverse scan, and 1 X 1 and 2 X 2 aggregation modes. Timing and biases are self generated by the multiplexer.
Infrared Technology XVIII | 1993
Thomas E. Wilson; Timothy F. Henricks; James Halvis; Brett D. Rosner; Robert R. Shiskowski
A large area infrared focal plane array was designed for use in a variety of military, dual- mode and commercial applications requiring high sensitivity and resolution. A high performance CMOS switched FET readout multiplexer was developed using standard foundry compatible processing. The array can be operated at frame rates up to 240 Hz in either snapshot or rolling readout mode. Independent variable integration control is included for either mode. Array size is logic selectable to either video format compatible 320 X 240, standard 256 X 256, or the entire 320 X 256. Data is read out sequentially through logic selectable 1, 2 or 4 outputs. A line array mode is included, any line selectable, with variable integration time up to 85% of line time. Each 31 micrometers X 31 micrometers cell has > 2.0 E7 electron integration well, coupled to the output via a charge drain sample and hold to maximize performance and to provide a continuous data stream. On chip bias generation, timing generation and level shifters minimize drive requirements. The silicon multiplexer was hybridized to a InSb detector array for a MWIR imaging demonstration.
Proceedings of SPIE | 1992
Timothy F. Henricks; Thomas E. Wilson; D. R. Bishop; James Halvis; Robert R. Shiskowski
This paper details a high performance MWIR scanning array with 30 time delay and integration stages (TDI), forward and reverse scan operation, less than 80 noise electrons per stage, and on focal plane blooming control and dynamic range compression. The 92 column by 30 TDI device is fabricated using hybrid technology with the detector fabricated in InSb and indium bumped to a VLSI/CMOS/CCD silicon readout fabricated in 1.25 micrometers CMOS with two poly and three metal interconnect levels.
Archive | 1991
James Halvis; Timothy F. Henricks; Thomas E. Wilson
Archive | 1991
James Halvis
Archive | 2006
James Halvis; Richard Mckee
Archive | 1986
Nathan Bluzer; James Halvis
Archive | 1987
James Halvis; Nathan Bluzer; Robert R. Shiskowski
Archive | 1997
Nathan Bluzer; James Halvis
Archive | 2011
Richard Mckee; Richard Madonna; Perry Fath; James Halvis