James J. Bonanno

Two level bulk preload branch prediction

This paper describes the large capacity hierarchical branch predictor in the 5.5 GHz IBM zEnterprise EC12 microprocessor. Performance analyses in a simulation model and on zEC12 hardware demonstrate the benefit of this hierarchy compared to a smaller one level predictor. Novel structures and algorithms for two level branch prediction are presented. Prediction information about multiple branches is bulk transferred from the second level into the first upon detecting a perceived miss in the first level. The second level does not directly make branch predictions. Access to the second level is limited when it is unlikely to be productive. The second level is systematically searched in an order that is likely to provide hits as early as possible. On the workloads analyzed in the simulation model, measurements show a maximum core performance benefit of 13.8%. On the two workloads analyzed on zEC12 hardware 3.4% and 5.3% system performance improvements are achieved.

The IBM z13 multithreaded microprocessor

The IBM z13™ system is the latest generation of the IBM z Systems™ mainframes. The z13 microprocessor improves upon the IBM zEnterprise® EC12 (zEC12) processor with two vector execution units, higher instruction execution parallelism, and a simultaneous multithreaded (SMT) architecture that supports concurrent execution of two threads. These advances yield performance gains in legacy online transaction processing and business analytics workloads. This latest generation system features an eight-core processor chip, a robust cache hierarchy, and large multiprocessor system design optimized for enterprise database and transaction processing workloads. The microprocessor core features a wide super-scalar, out-of-order pipeline that can sustain an instruction fetch, decode, dispatch, and completion rate of six z/Architecture® instructions per cycle. The instruction execution path is predicted by multi-level branch direction and target prediction logic. Complex instructions are split into two or more simpler micro-operations. Instructions are issued out of program order from an instruction issue queue to multiple RISC (reduced instruction set computer) execution units. The super-scalar design can sustain an issue and execution rate of ten micro-operations per cycle: two load/store type instructions, four fixed point (integer) instructions, two floating point or vector instructions, and two branch instructions.