James J. Curtin

Minimizing path delay in a machine by compensation of timing through selective placement and partitioning

Method, System and Storage Medium for Determining Circuit Placement

Active resistor trimming by differential annealing

Methods for placement which maintain optimized behavior, while improving wireability potential

Logic redundancy circuit scheme

Chip Having Timing Analysis of Paths Performed Within the Chip During the Design Process

Negative slack recoverability factor—a net weight to enhance timing closure behavior

Genie: a method for classification and graphical display of negative slack timing test failures

METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATION AND SLACK CATEGORIZATION

System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential