James L. Schwing

Broadcast-efficient protocols for mobile radio networks

The main contribution of this work is to present elegant broadcast-efficient protocols for permutation routing, ranking, and sorting on single-hop Mobile Radio Networks with p stations and k radio channels, denoted by MRN(p,k). Clearly, any protocol performing these tasks on n items must perform /sup n///sub k/ broadcast rounds because each item must be broadcast at least once. We begin by presenting an optimal off-line permutation routing protocol using /sup n///sub k/ broadcast rounds for arbitrary k, p, and n. Further, we show that optimal on-line routing can be performed in /sup n///sub k/ broadcast rounds, provided that either k=1 or p=n. We then go on to develop an online routing protocol that takes 2/sup n///sub k/+k-1 broadcast rounds on the MRN(p,k), whenever k/spl les//spl radic//sup p///sub 2/. Using these routing protocols as basic building blocks, we develop a ranking protocol that takes 2/sup n///sub k/+o(/sup n///sub k/) broadcast rounds as well as a sorting protocol that takes 3/sup n///sub k/+o(/sup n///sub k/) broadcast rounds, provided that k /spl epsiv/ o(/spl radic/n) and p=n. Finally, we develop a ranking protocol that takes 3/sup n///sub k/+o(/sup n///sub k/) broadcast rounds, as well as a sorting protocol that takes 4/sup n///sub k/+o(/sup n///sub k/) broadcast rounds on the MRN(p,k), provided that k/spl les//spl radic//sup p///sub 2/ and p /spl epsiv/ o(n). Featuring very low proportionality constants, our protocols offer a vast improvement over the state of the art.

Optimal parallel algorithms for problems modeled by a family of intervals

A family of intervals on the real line provides a natural model for a vast number of scheduling and VLSI problems. Recently, a number of parallel algorithms to solve a variety of practical problems on such a family of intervals have been proposed in the literature. The authors develop computational tools and show how they can be used for the purpose of devising cost-optimal parallel algorithms for a number of interval-related problems, including finding a largest subset of pairwise nonoverlapping intervals, a minimum dominating subset of intervals, along with algorithms to compute the shortest path between a pair of intervals and, based on the shortest path, a parallel algorithm to find the center of the family of intervals. More precisely, with an arbitrary family of n intervals as input, all the algorithms run in O(log n) time using O(n) processors in the EREW-PRAM model of computation. >

Optimal convex hull algorithms on enhanced meshes

In this paper we propose time-optimal convex hull algorithms for two classes of enhanced meshes. Our first algorithm computes the convex hull of an arbitrary set ofn points in the plane inO (logn) time on a mesh with multiple broadcasting of sizen×n. The second algorithm shows that the same problem can be solved inO (1) time on a reconfigurable mesh of sizen×n. Both algorithms achieve time lower bounds for their respective model of computation.

A fast selection algorithm for meshes with multiple broadcasting

One of the fundamental algorithmic problems in computer science involves selecting the kth smallest element in a collection A of n elements. We propose an algorithm design methodology to solve the selection problem on meshes with multiple broadcasting. Our methodology leads to a selection algorithm that runs in O(n/sup 1/8/(log n)/sup 3/4/)) time on a mesh with multiple broadcasting of size n/sup 3/8/(log n)/sup 1/4//spl times/n/sup 5/8//(log n)/sup 1/4/. This result is optimal over a large class of selection algorithms. Our result shows that just as for semigroup computations, selection can be done faster on suitably chosen rectangular meshes than on square meshes. >

SIMULATING ENHANCED MESHES, WITH APPLICATIONS

The purpose of this paper is to present non-trivial lower bounds for two classes of enhanced meshes. To achieve this goal we present efficient simulations of these two classes of enhanced meshes on the CREW-PRAM and Common-CRCW. From this, known computational lower bounds for the PRAM are transferred to the enhanced meshes. Our approach of transferring lower bounds from the PRAM to enhanced meshes is novel. Specifically, we show that any computation that takes O(t(n)) steps on an n-processor mesh with multiple broadcasting can be performed in O(t(n)) steps on an n-processor CREW-PRAM with O(n) extra memory. Similarly, with α standing for the inverse Ackermann function, we show that any computation that takes O(t(n)) computational steps on an n-processor basic reconfigurable mesh can be performed in O(α(n)t(n)) computational steps on an n-processor Common-CRCW with O(n) extra memory. We also show that some of the lower bounds that we derive are tight by providing matching upper bounds; as an example, we sh...

A Novel Deterministic Sampling Scheme with Applications to Broadcast-Efficient Sorting on the Reconfigurable Mesh

The main contribution of this work is to present a simple deterministic sampling strategy that, when used for bucket sorting, yields buckets that are remarkably well balanced, making costly balancing unnecessary. To the best of our knowledge, this is the first instance of a deterministic sampling strategy featuring this performance. Although the strategy is perfectly general, we illustrate its power by devising a VLSI-optimal,O(1) time sorting algorithm for the reconfigurable mesh. As a by-product of the inherent simplicity of our sampling and bucketing scheme, we show that our sorting algorithm can be implemented using only 35 broadcast operations, a substantial improvement over the previously best known algorithm that requires 59 broadcasts.

Visual and Spatial Analysis

This chapter provides a conceptual link between the decision making process, visualization, visual discovery, and visual reasoning. A structural model of the decision making process is offered along with the relevant visual aspects. Examples of USS Cole incident in 2000 and the Cholera epidemic in London in 1854 illustrate the conceptual approach. A task-driven visualization is described as a part of the decision making process and illustrated with browsing and search tasks.

Scalable hardware-algorithms for binary prefix sums

We address the problem of designing efficient and scalable hardware-algorithms for computing the sum and prefix sums of a w/sup k/-bit, (k/spl ges/2), sequence using as basic building blocks linear arrays of at most w/sup 2/ shift switches, where w is a small power of 2. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most w/sup 2/. We adopt a VLSI delay model where the length of a bus is proportional with the number of devices on the bus. We begin by discussing a hardware-algorithm that computes the sum of a w/sup k/-bit binary sequence in the time of 2k-2 broadcasts, while the corresponding prefix sums can be computed in the time of 3k-4 broadcasts. Quite remarkably, in spite of the fact that our hardware-algorithm uses only linear arrays of size at most w/sup 2/, the total number of broadcasts involved is less than three times the number required by an ideal design. We then go on to propose a second hardware-algorithm, operating in pipelined fashion, that computes the sum of a kw/sup 2/-bit binary sequence in the time of 3k+[log/sub w/ k]=3 broadcasts. Using this design, the corresponding prefix sums can be computed in the time of 4k+[log/sub w/ k]-5 broadcasts.

Fast computer vision algorithms for reconfigurable meshes

A bus system that can change dynamically to suit computational needs is referred to as reconfigurable. The authors are interested in obtaining fast algorithms for a number of low-level vision tasks on a two-dimensional mesh augmented with a reconfigurable bus system (reconfigurable mesh). Specifically, for an n*n digitized image stored one pixel per processor they present O(loglogn) algorithms to compute low-level descriptors including perimeter, area, histogram, median row, center as well as several moments.<<ETX>>

ON THE POWER OF TWO-DIMENSIONAL PROCESSOR ARRAYS WITH RECONFIGURABLE BUS SYSTEMS

Quite recently it has been proved that a two-dimensional processor array with a reconfigurable bus system (PARBS, for short) is at least as powerful as the CRCW shared memory computer. In this note we argue that the well-known PARITY problem can be solved in O(1) time on a two-dimensional PARBS of (n+1)×n processors. Since it is known that PARITY cannot be solved in constant time on a CRCW even if a polynomial number of processors is available, our result shows that the two-dimensional PARBS is strictly more powerful than the CRCW.