James N. Sweet

Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method

We report the first measurements of in-situ flip-chip assembly mechanical stresses using a CMOS piezoresistive test chip repatterned with a fine pitch full area array. A special printed circuit board substrate was designed at Sandia and fabricated by the Hadco Corp. The flip-chip solder attach (FCA) and underfill was performed by a SEMATECH member company. The measured incremental stresses produced by the underfill are reported and discussed for several underfill materials used in this experiment. A FEM of a one-quarter section of the square assembly has been developed to compare with the measured as-assembled and underfill die surface stresses. The initial model utilized linear elastic constitutive models for the Si, solder, underfill, and PC board components. Detailed comparisons between theory and experiment are presented and discussed.

Short and long loop manufacturing feedback using a multisensor assembly test chip

A family of silicon test chips for use in making diagnostic measurements during electronics assembly has been developed. These assembly test chips (ATCs) contain sensors that measure a number of variables associated with assembled IC degradation, including the degree of integrated circuit (IC) corrosion, handling damage, electrostatic discharge threat, moisture or humidity, mechanical stress, mobile ion density, bond pad cratering, and high-speed logic degradation. The chips in the ATC family are intended to give manufacturing feedback in four ways: direct feedback in evaluation of an assembly manufacturing line in an objective, nonintrusive way; before and after comparisons on an assembly production line when an individual process, material, or piece of equipment has been changed; resident lifetime monitor for system package aging and ongoing reliability projection; and thermal, mechanical, DC electrical, and high-frequency mock-up evaluation of packaging (including multichip) schemes. >

Liquid encapsulant and uniaxial calibration mechanical stress measurement with the ATC04 assembly test chip

A new assembly test chip, ATC04, designed to measure mechanical stresses at the die surface has been built and tested. This CMOS chip, 0.25 in. on a side, has an array of 25 piezoresistive stress sensing cells, four resistive heaters and two ring oscillators. The ATC04 chip facilitates making stress measurements with relatively simple test equipment and data analysis. The design, use, and accuracy of the chip are discussed and initial results presented from three types of stress measurement experiments: four-point bending calibration, single point bending of a substrate with an ATC04 attached by epoxy, and stress produced by a liquid epoxy encapsulant.<<ETX>>

PECVD silicon and nitride postbond films for protecting bondpads, bonds and bondwires from corrosion failure

It was demonstrated experimentally that the ultimate strain of PECVD thin-film silicon nitride coatings increased as the films were made thinner, giving them better mechanical properties for protecting underlying bulk Al structures such as bondwires, bond, and bondpads. In sections of under a micron, the films did not crack over Al bonds or bondwires during standard industrial temperature cycling. Temperature ramping tests indicated that 1000-A films had at least three times the ultimate strain expected from bulk values. Film thickness was consistent around bondwires and in the vicinity of the bonds from the plasma deposition. The most susceptible part of the films was the area in the occluded cavity under the foot of the bond. The spread of Al metallization corrosion under these films proceeded at a slower rate than the thinner films due to their more favorable mechanical properties. The results of this project indicate that PECVD silicon nitride films are good candidates as protective films for mounted and bonded microelectronic or hybrid devices and have the potential of outperforming polymeric films by a wide margin.<<ETX>>

Reliability of aluminum-nitride filled mold compound

There are increasing demands placed on plastic packages to dissipate higher power levels and operate in high temperature conditions. Of concern is the reliability and the functionality of the IC device operating at higher power levels and/or high temperature conditions. One particular concern is the integrity of the aluminum-gold wire bond interface under high operating conditions. Mold compound stability is one of several factors contributing to the stability of the aluminum-gold bond. The Plastic Packaging Consortium (PPC), a Technology Reinvestment Project (TRP) funded by DARPA under SOL 94-27, addresses the needs to build-up and strengthen an onshore infrastructure for thermally-enhanced, ruggedized, and high density packages. An 160-lead (28/spl times/28/spl times/3.4 mm) plastic quad flat pack (PQFP) is used to characterize a thermally-enhanced and high operating temperature stable mold compound. The compound uses silica-coated aluminum nitride (AlN) filler to provide a thermal conductivity 4-6 X compared to fused silica-filled compounds. Thermal measurements show the AlN compound decreases /spl theta//sub JA/ by 8-10/spl deg/C/W compared to the fused silica-filled molded package. The thermal performance of the AlN-molded packages is equal to the embedded heat spreader enhancements. Use of alternate flame retardant synergists (antimony pentoxide-Sb/sub 2/O/sub 5/-or a new non-antimony type) provide a more stable compound as determined by High Temperature Storage Life (HTSL) testing at 200/spl deg/C. The testing confirms that the compounds formulated with the alternate flame retardant synergists (Sb3/sub O5/ or non-antimony type) improve HTSL performance.

HAST evaluation of organic liquid IC encapsulants using Sandia's assembly test chips

Accelerated aging (HAST) experiments were conducted with special-purpose corrosion test chips (ATCs) in both bare die form and with various liquid encapsulants: epoxy, silicone and silicone elastomer, or silicone gel. The purpose of the experiment was to show what incremental improvement in die corrosion resistance was provided by the encapsulants and to determine the failure modes for the two types of samples. The test conditions were 140 degrees C/85% RH (relative humidity) and +40-V bias on outer tracks with respect to the center track. In the case of nonencapsulated parts, median lifetimes of about 1000 h were observed for the best passivations, with the predominant failure mode being triple track corrosion on the die. In the case of the encapsulated parts, the failure mode depended on the encapsulant type. Several of the silicone gel materials showed excellent HAST (high accelerated stress testing) performance, with only a few percent failures at the 1 100-h point.<<ETX>>

High Accuracy Die Mechanical Stress Measurement with the ATC04 Assembly Test Chip

A new Assembly Test Chip, ATC04, designed to measure mechanical stresses at the die surface has been built and tested. This CMOS ch@, 0.25 in. on a side, has an array of 25 piezoresistive stress sensing cells, four resistive heaters and two ring oscillators. The ATCO4 chip facilitates making stress measurements with relatively simple test equipment and data analysis. The design, use, and accuracy of the chip are discussed and initial results are presentedfiom three types of stress measurement experiments: four-point bending calibration, single point bending of a substrate with an ATC04 attached by epoxy, and stress produced by a liquid epoxy encapsulant.

Demonstration of a High Heat Removal Cvd Diamond Substrate Edge-Cooled Multichip Module

A single substrate intended for a 3-dimensional (3D) edge-cooled multichip module (MCM) has been built and thermally tested. The substrate, with dimensions 1.9 in. by 2 in., is mounted in a fluid cooled block at one end. To test this cooling architecture and verify the accuracy of thermal models, we constructed thermal test modules using alumina (Al/sub 2/O/sub 3/), aluminum nitride (AIN), and CVD diamond substrate materials. Each module was populated with an array of 16 Sandia ATC03 test chips with resistive heaters and temperature sensing diode thermometers. Comparative measurements of the 3 substrates were made in which the top row of 4 die were heated at 5 W each for a total of 20 W. The maximum temperature differences between the heated die and the interface with the cold chuck, /spl Delta/T/sub JS/, were 24, 126, and 265/spl deg/C for diamond, AIN and Al/sub 2/O/sub 3/, respectively. Measurements on the diamond thermal test module, uniformly heated at a total power of 45 W, gave a measured substrate-to-sink temperature of /spl Delta/T /spl AP/ 20/spl deg/C. An extrapolation of our experimental data indicates that the diamond edge-cooled substrate could dissipate a total power /spl AP/ 192 W for a maximum junction-to-ambient temperature of /spl Delta/T/sub JA/ /spl AP/ 124/spl deg/C. If multiple substrates were 3 mounted in the fluid cooled block, spaced 0.075 in. apart, the volumetric power density would be about 850 W/in/sup 3/.

IC chip stress during plastic package molding

Approximately 95% of the worlds integrated chips are packaged using a hot, high pressure transfer molding process. The stress created by the flow of silica powder loaded epoxy can displace the fine bonding wires and can even distort the metallization patterns under the protective chip passivation layer. In this study we developed a technique to measure the mechanical stress over the surface of an integrated circuit during the molding process. A CMOS test chip with 25 diffused resistor stress sensors was applied to a commercial lead frame. Both compression and shear stresses were measured at all 25 locations on the surface of the chip every 50 milliseconds during molding. These measurements have a fine time and stress resolution which should allow comparison with computer simulation of the molding process, thus allowing optimization of both the manufacturing process and mold geometry.

Liquid encapsulant stress variations as measured with the ATCO4 assembly test chip

We have examined the use of the ATCO4 piezoresistive Assembly Test Chip to measure the mechanical surface stresses produced by liquid encapsulation of die mounted directly on ceramic substrates. In our experiment, two groups of parts, each with about 70 samples, were encapsulated with two different materials, one a standard and one a low stress formulation. Results are presented for the measured stress components; /spl sigma//sub xx/-/spl sigma//sub zz/, /spl sigma//sub xy/, and /spl sigma//sub xx/-/spl sigma//sub yy/. We observe an /spl ap/20% reduction in the compressive stress between the normal stress and low stress materials, and a small but measurable difference in the average in-plane shearing stress. This experiment demonstrates the ability to resolve stress differences produced by different encapsulants and provides guidelines for selecting appropriate sample sizes.