James Prendergast

TDDB characterisation of thin SiO/sub 2/ films with bimodal failure populations

The paper deals with the extensive characterisation of a 20-nm oxide using multiple wafer fabrication lots. The data generated indicate that the intrinsic wearout properties of the oxide are best modelled by the E model with a field-dependent activation energy and a constant field acceleration factor. Of the 3 lots used in the characterisation one exhibited bimodal characteristics with a large extrinsic population. This allowed the investigation of the extrinsic distribution separately which exhibited a 1/E dependence and a field-dependent activation energy. The paper shows that using censored data for bimodal distributions results in the incorrect model (1/E) being used to predict intrinsic wearout. The paper also shows that in order to differentiate between the two models sample sizes must be run to 100% failure to ensure that true intrinsic wearout has been observed. The characterisation matrix used in the evaluation was very comprehensive and indicates E-fields of 7 MV/cm and below must be used to determine the correct field acceleration model.

Investigation into the correct statistical distribution for oxide breakdown over oxide thickness range

A critical aspect of integrated circuit manufacturing is the reliability of the components, in particular the gate oxide of transistors and capacitors. There are two statistical distributions, which can be applied to accelerated stress test failure data, namely the Lognormal or the Weibull distributions. The failure data can fit each distribution equally well. However both distributions will give vastly different lifetime predictions and their correct use is crucial for accurate lifetime prediction. A statistical based test, developed with Monte Carlo data, which is designed to decide if a failure data set has an underlying Lognormal or Weibull distribution is applied to empirical Time Dependent Dielectric Breakdown (TDDB) failure tests. The TDDB tests are carried out on 7 nm, 15 nm and 20 nm thick gate oxides. The results generated show the importance of making the correct choice between the two distributions for accurate lifetime prediction and validate the test for different oxide thickness. Also investigated are the effects of choosing the incorrect statistical distribution has on the voltage and temperature acceleration factors.

Building‐in reliability ‐ implementation and benefits

Argues that in the coming years the present methods of demonstrating reliability will no longer be feasible and alternative methods must be found. Deals with building‐in reliability (BIR) and the necessity to change from the standard end‐of‐line‐measurement technique of life test to a more proactive in‐line approach, where reliability can be measured by process parameters and reaction time is immediate, resulting in a continuous flow of reliable product to the end user. This approach will not eliminate the use of end‐of‐line monitoring, but will reduce the amount which needs to be carried out. Suggests that it will only be done to demonstrate that processes are operating to certain maximum failure rates, where the online controls will in fact guarantee that the reliability is much greater than that being demonstrated. Examines the customers’ attitude towards reliability, and points out that sharing of data will be essential if the BIR approach is to be successful. Outllines two examples which demonstrate the effectiveness of a BIR program and explains how, if implemented, it can be used to prevent the manufacture of potentially unreliable product.

A technique to predict gate oxide reliability using fast on-line ramped Q/sub BD/ testing

Various methods of measuring the dielectric integrity of gate oxide to qualify wafer fabrication foundries have developed over time. Test durations range from seconds to hours depending on the conditions used and applied. There is a view that the longer the test duration the more accurate the reliability prediction. The cost and delays associated with the lengthy package level TDDB (time dependent dielectric breakdown) test have resulted in it being applied less often and being replaced by wafer level tests. This paper evaluates two methods of wafer level tests, namely: ramped Q/sub BD/ testing applying a fixed initial current (as generally used in the production environment); ramped Q/sub BD/ testing applying a fixed initial current density (more commonly reported in the literature). The above tests are compared to the package level constant voltage TDDB test. This paper provides a thorough investigation into the oxide area dependency for both Q/sub BD/ and TDDB tests. This paper also investigates the potential correlation between both the Q/sub BD/ and TDDB tests. Finally, these correlations are used to implement on-line control equations that can be utilised by manufacturing to quickly compare their Q/sub BD/ results to required product lifetimes.

Investigation of the intrinsic SiO2 area dependence using TDDB testing and model integration into the design process

Abstract This paper models the area dependency for thin SiO 2 films (1.2E-7 to lE-2 cm 2 ) using Time Dependent Dielectric Breakdown testing over a wide range of electric fields and test temperatures. The data generated indicates that the field and temperature acceleration factors are the same for all the areas tested indicating that the failure mechanism is the same even though the times to failure are different for all the area sizes. The paper will explain and model the area effect on TDDB lifetime and use the model to predict gate oxide reliability in the design cycle.

Predicting oxide reliability from in line process statistical reliability control

This paper demonstrates the applicability of the building in reliability approach by using a combination of experimental design techniques and test structures to relate in line SPC parameters to reliability. The experimental design techniques used to demonstrate the links between SPC and reliability were Taguchi and Response Surface Methodology Central Composite Face Centred Design. Of primary interest was modelling the intrinsic distribution and the secondary objective was modelling the total distribution to understand the causes of the extrinsic component of the total distribution. The Taguchi experiment was used initially as a screening experiment to select the SPC parameters which had the most critical effect on the intrinsic and extrinsic oxide reliability. Once these parameters were selected Central Composite Face Centred Design was used to generate another experiment with which to model the results. The results from this experiment indicate that the intrinsic reliability of the oxide could be predicted from in line process control parameters with 95% confidence. The extrinsic contribution to the reliability distribution was investigated by analysing the total distribution and modelling the results. In this instance it was possible to model the results with 99.5% confidence. In both cases models and response surfaces have been generated which are different for the 2 distributions analysed. The models were generated with the untransformed data and are highly quadratic. The paper introduces the concept of Statistical Reliability Control (SRC) and indicates that by using Statistical Reliability Control it is possible to monitor and predict the reliability of the gate oxide process on line in real time.

Predicting gate oxide reliability from statistical process control nodes in integrated circuit manufacturing — a case study

This paper investigates the possibility of transferring the concepts developed for SPC into reliability control of integrated circuits. It employs Taguchi methods and response surface methodology to predict the reliability of a 20 nm gate oxide process using selected critical in line parameters. A Taguchi L 12 design was used as a screening experiment to determine the most critical factors which effect the reliability of the gate oxide dielectric. From this three parameters were selected for use in a central composite face centred array to model their effect on the oxide dielectric reliability using response surface methodology. The reliability of the oxide dielectric was measured using time-dependent dielectric breakdown testing, and the calculations were based on the time to 0.1 per cent cumulative failure, as this is the time on which industry standard reliability predictions are based. The results show that using a test chip the intrinsic reliability of the oxide can be modelled using the values obtained from critical nodes within a wafer fabrication facility and that this is a viable approach to predict oxide reliability.

BIR-breaking down the barriers [building in reliability methodology for CMOS wafer fab]

A Building In Reliability (BIR) methodology was incorporated into the development of a sub-micron, double-poly double-metal (DPDM) CMOS wafer fabrication process. This new and proactive approach ensured a reliable process. A multi disciplined team effort was required to understand, control, and measure the critical process parameters which affect the process reliability and manufacturability. Wear out mechanisms of gate oxide integrity, hot electron induced MOSFET degradation, and electromigration were tested on individual process modules to ensure reliability. The benefits from using the BIR methodology are reduced qualification costs, earlier time to market, and greater confidence in process reliability.

Building In Reliability. Is Statistical Process Control Statistical Reliability Control

This paper deals with the concept of using experimental design to verify the ideals of building in reliability in an integrated circuit fabrication process. The paper focuses on the gate oxide loop, which is one of the most critical steps in the process and uses a combination of a linear L12 Taguchi Array and Central Composite Face Centred Design experimental techniques to prove the Building In Reliability concept. The work will demonstrate that from a quality perspective many nodes are controlled in the process but only certain nodes have an impact on reliability. If these nodes are carefully controlled reliability can be maintained and indeed predicted possibly by using an expert system thus leading to “Statistical Reliability Control”.

Relationship between TDDB testing and wafer level ramped QBD testing using both fixed current and current density stressing

Over the years various tests have been proposed for measuring the dielectric integrity of gate oxide. The duration of these tests can range from seconds to hours depending on the conditions used. Reliability purists maintain that the longer the test duration the more accurate the reliability prediction will be. Given that todays technologies are changing rapidly, it is not possible to devote large amounts of time to reliability testing. Therefore, wafer level tests are being used more and more often (as opposed to the lengthy package level TDDB test) to qualify wafer fabrication foundries. This paper investigates two types of wafer level ramped current Q/sub BD/ testing together with the package level constant voltage TDDB test. This paper provides a thorough investigation into the oxide area dependence for both Q/sub BD/ and TDDB tests. Finally, this paper investigates the potential correlation between the Q/sub BD/ and TDDB tests.