James R. Moulic

Cell/B.E. blades: building blocks for scalable, real-time, interactive, and digital media servers

The Cell Broadband Engine™ (Cell/B.E.) processor, developed jointly by Sony, Toshiba, and IBM primarily for next-generation gaming consoles, packs a level of floating-point, vector, and integer streaming performance in one chip that is an order of magnitude greater than that of traditional commodity microprocessors. Cell/B.E. blades are server and supercomputer building blocks that use the Cell/B.E. processor, the high-volume IBM BladeCenter® server platform, high-speed commodity networks, and open-system software. In this paper we present the design of the Cell/B.E. blades and discuss several early application prototypes and results.

HIGHLY PARALLEL COMPUTERS: PERSPECTIVES

Abstract Highly parallel machines represent a technology capable of providing superior performance for technical and commercial computing applications. By utilizing technical advances in microsystems, such as the high performance RISC processors, and high speed interconnect, together with progress in algorithms and compilers, massively parallel systems will exceed the limits of performance being approached by traditional vector supercomputers. Prototypes have been built at IBM Research over the past 10 years to test various approaches: YSE, the Yorktown Simulation Engine, was a high performance, special purpose machine for logic simulation. Today, descendants of this machine are in use at nearly every IBM Development Laboratory; the RP3, Research Parallel Processor Prototype, was an innovative shared-memory multi-processor of the multiple instruction multiple data (MIMD) type; GF11, is an enhanced single instruction multiple data (SIMD) machine that currently achieves the highest sustained performance on key applications; and Victor-V256, a distributed memory, fixed-grid interconnect MIMD machine with 256 processors. In this paper we present our views on the influence of personal computing and telecommunication technologies on parallel processing. We will describe where the architecture of future parallel computers is heading and identify several network and hardware design issues which affect parallel machine implementations. We will also describe some of the parallel machines recently built at the IBM T. J. Watson Research Center, and conclude by projecting the evolving use of parallel computing and the likely route parallel computing will take into the 21st century.

Incorporating benchmark programming in the teaching of undergraduate Computer Architecture

Advanced Computer Architecture is an upper-level required course offered by the Department of Computer Science and Engineering at the University of Alaska-Anchorage (UAA). Course content is structured to provide students with a qualitative and quantitative approach to computer architecture, which addresses both the hardware and software aspects of parallelism in modern computing systems. Historically, students were exposed to computer architectures hardware-centric concepts through traditional textbook publisher provided instructor materials, including system schematic and block diagrams, and cycle-by-cycle hand analysis of short assembly language code snippets. Recorded student achievement outcomes for the course, were just meeting the faculty defined levels. Analysis of student performance indicated a higher-level of course content understanding in students with a mix of both hardware and software skills, and lower achievement levels by those students with only software background and skills. In an attempt to improve overall student understanding and outcome achievement, a reform of course material presentation was initiated which focused on use of microbenchmark programming as a means of introducing selected computer hardware concepts through their programming interfaces. Most computer science students are good programmers and understand high-level languages and algorithms. As such, they are used to tackling new concepts with software, so it was hoped that by linking the instruction of computer architecture hardware concepts with a programmers perspective, overall student understanding and outcomes would improve.