James T. Doyle

A CMOS subbandgap reference circuit with 1-v power supply voltage

A CMOS subbandgap reference circuit with 1-V supply voltage is described. To obtain subbandgap reference voltages with a 1-V supply voltage, threshold voltage reduction and subthreshold operation techniques are used. Large /spl Delta/V/sub BE/ (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset. A power-on-reset (POR) circuit is used as startup. This circuit has been implemented using a standard 0.5-/spl mu/m CMOS process, and its size is 940 /spl mu/m/spl times/1160/spl mu/m. The temperature coefficient is 17 ppm from -40/spl deg/C to 125/spl deg/C after resistor trimming and the minimum power supply voltage is 0.95 V. The measured total current consumption is below 10 /spl mu/A and the measured output voltage is 0.631 V at room temperature.

An accurate DAC modeling technique based on wavelet theory

Two new DAC modeling techniques, based on principles of wavelet theory, are described in this paper. A macro model and mathematical model are developed for analog and digital circuit simulation, respectively, for fast and accurate results using an exponential function, damped sine wave, and linear waveform. An 8 bit DAC has been implemented to simulate and evaluate the models. The INLs of the macro and mathematical model based simulations are /spl plusmn/ 0.2 LSB, which are the same as HSPICE simulation. The DNLs of HSPICE simulation, macro model, and mathematical model based simulations are /spl plusmn/ 0.22 LSB, /spl plusmn/ 0.28 LSB, and /spl plusmn/ 0.25 LSB, respectively. The simulation times are 2.9 s for the macro model, 0.15 s for the mathematical model, and 68.09 s for the HSPICE simulation.

A low power CMOS CORDIC processor design for wireless telecommunication

A CORDIC processor for wire telecommunication is integrated in a 0.5 mum CMOS technology. The CORDIC (coordinate rotation digital computer) processor reduces the circuit complexity by performing a sequence of elementary rotations using shift and add operations without multiplications. Hard wired-logic eliminates the shifter and includes pre-calculated arctan angle values. The average power consumption is 76 mW with 50 MHz clock and 5 V power supply. The fabricated modulator consumes 24 mW at 61.44 MHz sampling rate and 5 V power supply.

A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control

A fully digital self-adjusting high efficiency power supply system has been developed based on an FSM control scheme. The system dynamically monitors circuit performance with a slacktime detector, and provides a substantially constant minimum-supply voltage for digital processors to properly operate at a given frequency with regard to different process-voltage-temperature (PVT) and load conditions. The digital FSM scheme significantly reduces the complexity of control loop implementation (<1800 gates) and its own power consumption (<100muW)

Fast and accurate DAC modeling techniques based on wavelet theory

Abstract Two new modeling techniques based on principles of wavelet theory are described in this article. Macro-model and mathematical model are developed for analog and digital circuit simulation, respectively, for fast and accurate results using exponential function, damped sine wave, and linear waveform. An 8 bit DAC has been implemented to simulate and evaluate the models. The INLs of the macro and mathematical model based simulations are ±0.2LSB, which are the same as HSPICE simulation. The DNLs of HSPICE simulation, macro model, and mathematical model based simulations are ±0.22LSB, ±0.28LSB, and ±0.25LSB, respectively. The simulation times are 2.9 s for macro model, 0.15 s for mathematical model, and 68.09 s for HSPICE simulation.