James Vincent Dilorenzo

Control of gate—Drain avalanche in GaAs MESFET's

The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, on the output power of GaAs FETs. In this paper we show that recognition of the role of surface depletion and proper attention to channel design can yield avalanche voltage factors of 2-3 above bulk values. The appropriate design strategy is minimization of the undepleted epitaxial charge per unit area (Qu) between gate and drain, which, in turn, dictates a gate-notch depth approximately equal to the surface zero-bias depletion depth. A simple lateral spreading model is proposed which predicts thatV_{L} \sim 50Q\min{u}\max{-1}, where VLis the gate-drain avalanche voltage and Quis measured in units of 1012electrons/cm2. This prediction is supported by a large body of experimental dc and pulse data, although considerable scatter is observed which we have attributed to epi charge nonuniformities, premature avalanche at the rough edges of AI gates formed by a liftoff process, and surface charging variations associated with dielectric passivation. The observed dependence of VLon epi charge rather than on doping level, as predicted for bulk avalanche, provides convincing evidence for nonbulk two-dimensional avalanche in the thin-film (Q_{u} < 2.3) FET geometry. In thick films (Q_{u} > 2.6), on the other hand, it is found that the bulk avalanche predictions are reasonably accurate. In terms of saturated epi current Is, the bulk regime corresponds toI_{s} > 450mA/mm and the lateral spreading (thin-film) regime toI_{s} < 400mA/mm. Finally, we have found that gate-drain avalanche is the major cause of output saturation as a function of drain potential in power GaAs FETs.

Long-term and instantaneous burnout in GaAs power FET's: Mechanisms and solutions

Catastrophic source-drain burnout is an important failure mode in GaAs power FETs. In this paper we show that short-term (instantaneous) and long-term (aging) failures have different physical origins provided the underlying drain ohmic-contact weakness has been suppressed by use of a recessed n+drain ledge geometry. With this drain configuration, instantaneous burnout is due to thermal runaway of the buffer/substrate when local temperatures reach the 500-550°C range. For our typical devices With 30-50-µm-thick substrates, the associated de burnout power is 4-5 W/mm of gate periphery. Long-term aging failure, on the other hand, results from chemical changes at the GaAs surface between gate and drain. These changes induce localized areas of avalanche white-light emission, particularly along the n+ledge, which serve as burnout precursors. A series of aging, surface etching, and passivation experiments has revealed that oxygen probably plays a major role in the aging process, perhaps through its known effect on free arsenic formation. Moreover, it is found that minimization of the oxygen content at the top surface by using si3N4:H passivation rather than SiO2not only prevents white-light emission but increases the median life at 310°C channel temperature from 2.5 to more than 500 h.

Reliability of power GaAs field-effect transistors

A preliminary report on a comprehensive study of the reliability of power GaAs FETs is presented, concerning the catastrophic burn-out failure and gradual degradation failure. The samples used are all 6-mm-wide devices with a nominal gate length of 2 micrometers. The life tests have been carried out at elevated channel temperatures of 250°C, 210°C, and 175°C, simultaneously, with samples of 16, 56, and 140, respectively, under dc bias conditions of 14-V drain-source voltage and 0.55-A drain current in all cases. Since the initiation of this program, none of the above 212 devices has burned out for a total of 730,000 device-hours at the time of this writing. Therefore, the failure rate at normal operational temperature can be predicted under various assumptions. An extremely slow degradation in the electrical parameters has been observed with the 250°C and 210°C tests. At the 175°C, no detectable deterioration has taken place so far. Using a new technique the gradual degradation symptom has been analyzed and possible mechanisms are pointed out. In addition, thermally accelerated life tests with a 4-GHz input of 0.63W have shown aging results comparable to those of the dc-bias-only cases.

Low‐noise and high‐power GaAs microwave field‐effect transistors prepared by molecular beam epitaxy

The low‐noise FET’s prepared on molecular‐beam‐epitaxial (MBE) layers have a noise figure of 1.9 dB with a corresponding gain of 11 dB at 6 GHz. The power FET’s can produce 1.3 W at 4.4 GHz (1‐dB compression) with a gain of 10 dB and a power‐added efficiency of 35%. The influence of substrate preparation on Hall mobility for very thin layers was also studied and there is no evidence of Cr diffusion from the substrate at the MBE growth temperature.

Nonalloyed and insitu Ohmic contacts to highly doped n‐type GaAs layers grown by molecular beam epitaxy (MBE) for field‐effect transistors

MBE was used to grow n‐type GaAs layers doped with tin to approximately 5×1019 cm−3. Au/Ge Ohmic contacts were formed on the heavily doped layers without exceeding the eutectic temperature, thereby producing a nonalloyed Ohmic contact. In an in situ metallization experiment, tin was deposited on a freshly grown n++ layer. The deposited contact (without any heating) has linear current‐voltage characteristics. Power GaAs FET’s were fabricated with nonalloyed Au/Ge contacts which showed excellent rf and dc characteristics. The combination of MBE n++ layer growth and the technology presented here may have potential for microwave devices and GaAs integrated circuits.

Electrolytic etching and electron mobility of GaAs for FET's

Abstract An electrolytic etching technique for n-GaAs is presented. The procedure is applied to post-growth etching of FET wafers to achieve uniformly thin layers from excessively thick and nonuniform material. Measurements on a Hall sample, thinned by this technique, show mobilities in good agreement with theoretical bulk mobility calculations for films as thin as 2100 A. From Hall measurements on layers covered by the anodic native oxide, it is determined that the oxide interface traps 3·9 × 1011 electrons per cm2 more charge than the as-grown surface.

Selective lift-off for preferential growth with molecular beam epitaxy

Semiconducting material consisting of inlays of different doping or composition in selective areas may be grown by molecular beam epitaxy (MBE). The growth morphology showed that it is possible to fill an etched hole with MBE without the formation of voids resulting from facet growth as observed in other growth techniques. This regrowth process may have potential for applications to integrated microwave and optoelectric devices.

Reliability of Improved Power GaAs Field-Effect Transistors

Some 270 6-mm power GaAs FETs with aluminum gates and silicon-nitride passivation have been aged at elevated channel temperatures under dc-bias with or without rf-drive. One catastrophic burnout and extremely slow degradation have been observed for 2-million device-hours. Tentatively estimated failure rates for burnout and for gradual degradation at a maximum channel temperature in normal operation of 110°C are both well below 100 FITs. This represents an improvement of at least one order of magnitude over previous devices whose reliability is presented in a companion paper1. In the improved model no deterioration in gates and ohmic contacts has been observed. Gradual degradation has been caused by deterioration in the channel material. However, this has been an extremely slow process, giving rise to practically no problem. There has been no difference in gradual degradation between devices aged with and without rf-drive for 6,000 hours at 250°C channel temperature. The present study has already. demonstrated that the power GaAs FETs used as the samples are very reliable.

Beam-Lead plated heat sink GaAs IMPATT: Part I&#8212;Performance

GaAs IMPATT devices are currently being developed for use as high-power microwave oscillators. Since low thermal impedance is required for dissipation of high input powers, this device is usually fabricated by thermal compression bonding to a diamond heat sink or a multimesa plated heat sink. This paper discusses the development of 4-mesa beam-leaded plated heat sink (BLPHS) C- and X-band GaAs IMPATT diodes. A description of the fabrication procedures is given, whereby the beam-lead interconnects are formed as part of the wafer fabrication procedure. Diodes tested at 5 GHz give up to 7.3 W of output power at 13.5- percent efficiency at a junction temperature of approximately 210°C. X-band diodes, although the data is more limited, show efficiencies up to 16.5 percent (2.2 W) for fiat profile diodes, and up to 20.8 percent for lo-hi-lo profile diodes. BLPHS diodes, therefore, are limited in their efficiency by the epitaxial materials doping profile. Accelerated stress aging data taken to date on BLPHS units show them to have an estimated mean time to failure greater than 2 × 106h at 200°C, which is comparable to thermal compression bonded to diamond units.