Jan Bartovsky

Pipeline architecture for compound morphological operators

In this paper we present a new pipeline HW architecture for fast 2-D erosions/dilations. The implementation is based on a recently proposed algorithm allowing to process 2-D data in a stream, minimizing the use of memory and drastically reducing the computing latency. These elementary operators can be chained in an efficient pipeline to realize compound morphological operators (opening, closing, ASF filters, etc.) with no intermediate image storage and minimal latency.

Implementation of AODV routing protocol in sensor wireless networks

This paper presents an implementation of the Ad hoc On-Demand Distance Vector (AODV) routing protocol in conditions of sensor wireless networks. AODV is a reactive on-demand distance vector protocol and utilizes partially connected mesh network topology. Designed stack is intended for purposes of applications that require quick adaptation to dynamic link conditions. Protocol implementation was primarily focused on embedded systems with constrained memory and computational resources and was intended to be easy portable to other platforms. For testing purposes, designed stack was attached to link layer of SimpliciTI stack and compiled for CC430 microcontroller with on-chip sub-1-GHz RF transceiver supplied by Texas Instruments Company. This work was motivated by the need of a simple implementation of the routing protocol intended for tiny systems and utilizing mesh network topology which will quickly adapt on fast node position changes.

SPECTRIG — Device for triggering and spectroscopy with the pixelated particle detector

The Article deals with the precise timed measurement using the advanced pixelated particle detector. There is described a design of the extra device Spectrig that is dedicated to generate the additional trigger signal which enables utilization of detector capabilities in the single particle tracking and spectroscopy applications. The article also describes how the Spectrig device performs signal processing and how it is implemented.

Stream implementation of serial morphological filters with approximated polygons

This paper describes an original stream implementation of serially composed morphological filters using approximated flat polygons. It strictly respects a sequential data access. Results are obtained with minimal latency while operating within minimal memory space; even for very large neighborhoods. This is interesting for serially composed advanced filters, such as Alternating Sequential Filters or granulometries. We show how the dedicated implementation on an FPGA allows obtaining a previously unequaled performance, opening an opportunity to use these operators in time-critical, high-end applications.

Compact device for detecting single event effects in semiconductor components

The paper describes a compact system for detecting Single Event Effects (SEE) in semiconductor components. The SEE is caused by a hit into a electronic chip with an energetic particle. The hit can cause unexpected behaviour of the system. The tested component is called Device Under Test (DUT). The structure of the system is shown and used components are described with their main tasks. Some of results of the running system are shown.

PLC communication in Smart Grid

At present, the vast majority of communication in smart grid is realized over the GSM/GPRS or Ethernet based protocols. Still, there is a possibility to use existing wires and transmit a low-rate data over power lines. No matter how much the cost to equip the grid with the new technology falls, the costs to service the instrumentation in the field are still not negligible. Moreover, the diversification of the communication channels could lead to system integration or standardization problems. This paper shows how the PLC communication can be used to improve robustness and efficiency when controlling the grid. It also points out a couple approaches to coupling circuits and impedance matching circuits based on previous experiences of the others. There are comments on the coupling transformers usage and their limitations. The paper also introduces a new concept of self-tune adaptive coupler with injection coil.

Overview of recent advances in hardware implementation of mathematical morphology

This paper surveys the state of the art of mathematical morphology from a perspective of algorithmic advances of the low-level morphological operators dilation and erosion as well as implementation of these algorithms in the dedicated hardware, such as FPGAs. The existing architectures are categorized in three groups: neighborhood processors, partial-result reuse, and efficient algorithm implementation. The performance of recent proposals was compared on an ASF filter application.

One-scan algorithm for arbitrarily oriented 1-D morphological opening and slope pattern spectrum

This paper presents a fast, one-scan algorithm for 1-D morphological opening on 2-D support. The algorithm is further extended to compute the pattern spectrum during a single image scan. The structuring element (SE) can be oriented under arbitrary angle that makes it possible to perform different orientation-involved image analysis, such as the local angle extraction, directional granulometry, etc. The algorithm processes an image in constant time regardless the SE orientation and size in one scan, with minimal latency and very low memory requirements. For pattern spectra, the C-implementation yields an experimental speed-up of 27× compared to other suitable solutions. Aforementioned properties allow for efficient implementation on hardware platforms such as GPU or FPGA that opens a new opportunity of parallel computation, and consequently, further speed-up.

Efficient FPGA architecture for oriented 1-D opening and pattern spectrum

This paper deals with a dedicated hardware architecture for 1-D morphological opening and pattern spectrum. These operators allow extraction and measurement of 1-D features in images that is a commonly used technique in image analysis and texture classification. The architecture is based on a recently proposed opening algorithm and makes it possible to obtain arbitrary-oriented opening and granulometry at the same time. Respecting a sequential data access, several instances with different orientation can run in parallel on a single input dataflow, increasing thus the performance (experimentally 414 Mpx/s per opening). It opens applicability of traditionally costly operators in embedded, industrial applications.

Morphological co-processing unit for embedded devices

Abstract This paper focuses on the development of a fully programmable morphological coprocessor for embedded devices. It is a well-known fact that the majority of morphological processing operations are composed of a (potentially large) number of sequential elementary operators. At the same time, the industrial context induces a high demand on robustness and decision liability that makes the application even more demanding. Recent stationary platforms (PC, GPU, clusters) no more represent a computational bottleneck in real-time vision or image processing applications. However, in embedded solutions such applications still hit computational limits. The morphological co-processing unit (MCPU) replies to this demand. It assembles the previously published efficient dilation/erosion units with geodesic units and ALUs to support a larger collection of morphological operations, from a simple dilation to serial filters involving a geodesic reconstruction step. The coprocessor has been integrated into an FPGA platform running a server that is able to respond to client’s requests over the ethernet. The experimental performance of the MCPU measured on a wide set of operations brings as results in orders of magnitude better than another embedded platform, built around an ARM A9 quad-core processor.