Jan Langer

New Methods and Coverage Metrics for Functional Verification

An ever increasing portion of design effort is spent on functional verification. The verification space as the set of possible combinations of a designs attributes is likely to be very large making it infeasible to verify each point in this space. State-of-the-art verification tools tackle this problem by using directed random generation of combinations in conjunction with manually defined corner cases in order to get satisfactory coverage with the desired distribution. In this work, the underlying methodology to automatically generating complete sets of disjoint coverage models on the basis of formal attribute definitions is extended to take relational constraints into account. This allows the utilization of coverage models with non-orthogonal, non-planar boundaries, which can make whole analysis for coverage data obsolete. It shall be demonstrated, how the proposed methodology can be used to automatically determine corner cases more accurately than it is possible with conventional approaches

Hardware implementation of a Particle Filter for location estimation

In this paper we present the hardware implementation of a Particle Filter for location estimation. Based on distance information to static network nodes, the filter estimates the three-dimensional position of a mobile network node. The design has been derived from a set of formal operation properties and synthesized for an FPGA prototype platform. Accessed through a serial interface, it can be used as a location estimation core from microcontrollers with low computational power. The implemented models for state transition and measurements can be re-parameterized during operation. Due to the chosen design approach these models can also easily be modified or exchanged in order to match the application needs. The correct functionality of the implementation has been shown using real time-of-flight based distance measurements. Therefore, the prototype platform has been integrated in an existing IEEE 802.15.4a compliant wireless network infrastructure.

A platform for requirement based formal specification

Formal executable specification is one in the ITRS 2007 design report proposed solution to handle future design challenges. Specifications have to be checked for completeness and consistence. Furthermore, it is desirable to support later design steps by generating descriptions for simulation and synthesis, properties for simulative and formal verification and testing scripts. This can be achieved by using formal specification. During development the results of the design steps have to be fed back in the specification tool in order to track changes and the progress of the development. In this paper we present a specification tool which combines formal specification with requirements engineering to achieve a consistent and traceable specification.

Automatic Visualization of Abstract System Specifications

Complexity of hardware/software systems is continuously increasing. Formal specification is a methodology to ensure better quality of system specifications and to allow automated verification with tools like model checkers. Many formal specification approaches are known - ranging from programming languages to graphical specification tools. Each approach has its specific benefits. Usually, for abstract system and software specifications either table based or graphical notations are used. This paper presents a concept that leverages the advantages of both approaches by combining them in a single front-end. Both the table based and the graphical representation may be used for editing the specification. An automatic synchronization mechanism ensures that both representations are kept consistent. The implementation of the concept uses the table based formal language ADeVA and the Graphviz graph layout programs

Demonstration of an in-band reconfiguration data distribution and network node reconfiguration

This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configuration data marked by the EtherType field in the Ethernet header. For evaluation the application is implemented on a prototype consisting of two XILINX FPGA boards. Since the target platform is an ASIC with embedded reconfigurable architectures the prototype is divided in the corresponding parts. One board emulates the embedded reconfigurable architecture that contains the Ethernet MAC. Ethernet packets can reconfigure this MAC. The second board emulates the static part of the application that controls the reconfiguration process.

High level synthesis using operation properties

We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval Language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties as a design method is the existence of commercial tools to check the completeness and consistency of the property set. Furthermore, operation properties are well suited for specifications of consecutive operations of finite length. We show the practicality of our method by implementing a particle filter for a localization application.

Tracking of Mobile Nodes in Sensor Networks

We present the development and implementation of an algorithm for tracking the position of a mobile network node. The tracking algorithm uses distance measurements between a mobile node and multiple anchor nodes. The first stage of our algorithm calculates the initial position from distance measurements relative to three (2D) or four (3D) anchors of known position. In a second stage this initial position is improved and tracked over time by feeding a Kalman filter with new distance measurements to neighboring anchor nodes of known position. Both the algorithm and the related communication protocol have been implemented and verified in multiple scenarios by using the event driven OMNET++ network simulator.

Finding an optimal set of breakpoint locations in a control flow graph

With the advance of high-level synthesis methodologies it has become possible to transform software tasks, typically running on a processor, to hardware tasks running on a FPGA device. Furthermore, dynamic reconfiguration techniques allow dynamic scheduling of hardware tasks on an FPGA area at runtime. Combining these techniques allows dynamic scheduling across the hardware-software boundary. However, to interrupt and resume a task, its context has to be identified and stored. We propose a method to find an optimal set of breakpoints in the control flow of a hardware task, such that the introduced resource overhead for context access is minimized and a maximum latency between interrupt request and the end of the context storing is guaranteed. This set of breakpoints allows the context to be restricted to the essential subset of data. Our method opens the door to flexible task scheduling not only on one reconfigurable device but also between different devices and even software instances of the same task.

Improved Coverage Driven Verification and Corner Case Analysis using Decision Diagrams

An ever-increasing portion of design effort is spent on functional verification. The verification space as the set of possible combinations of a designs attributes is likely to be very large making it infeasible to verify each point in this space. State-of-the-art verification tools tackle this problem by using directed random generation of combinations in order to get satisfactory coverage with the desired distribution. The main drawback of using random generators is that increasing coverage grade demands lead to an exponential growth in runtime. As remedy to this deficiency coverage driven verification strategies were proposed generating only combinations not covered so far. Unfortunately, this cannot completely solve the problem since usually an arbitrary combination is generated which is then checked for previous coverage. In this work, decision diagrams are used to represent the set of valid combinations inside the complete verification space. Based on this analytical model, any number of combinations can be generated in linear time. Applied to coverage driven verification, this methodology leads to random generation orders of magnitudes faster than conventional approaches