Jan M. Rabaey

A study of low level vibrations as a power source for wireless sensor nodes

Advances in low power VLSI design, along with the potentially low duty cycle of wireless sensor nodes open up the possibility of powering small wireless computing devices from scavenged ambient power. A broad review of potential power scavenging technologies and conventional energy sources is first presented. Low-level vibrations occurring in common household and office environments as a potential power source are studied in depth. The goal of this paper is not to suggest that the conversion of vibrations is the best or most versatile method to scavenge ambient power, but to study its potential as a viable power source for applications where vibrations are present. Different conversion mechanisms are investigated and evaluated leading to specific optimized designs for both capacitive MicroElectroMechancial Systems (MEMS) and piezoelectric converters. Simulations show that the potential power density from piezoelectric conversion is significantly higher. Experiments using an off-the-shelf PZT piezoelectric bimorph verify the accuracy of the models for piezoelectric converters. A power density of 70 @mW/cm^3 has been demonstrated with the PZT bimorph. Simulations show that an optimized design would be capable of 250 @mW/cm^3 from a vibration source with an acceleration amplitude of 2.5 m/s^2 at 120 Hz.

Energy aware routing for low energy ad hoc sensor networks

The recent interest in sensor networks has led to a number of routing schemes that use the limited resources available at sensor nodes more efficiently. These schemes typically try to find the minimum energy path to optimize energy usage at a node. In this paper we take the view that always using lowest energy paths may not be optimal from the point of view of network lifetime and long-term connectivity. To optimize these measures, we propose a new scheme called energy aware routing that uses sub-optimal paths occasionally to provide substantial gains. Simulation results are also presented that show increase in network lifetimes of up to 40% over comparable schemes like directed diffusion routing. Nodes also burn energy in a more equitable way across the network ensuring a more graceful degradation of service with time.

PicoRadio supports ad hoc ultra-low power wireless networking

Technology advances have made it conceivable to build and deploy dense wireless networks of heterogeneous nodes collecting and disseminating wide ranges of environmental data. Applications of such sensor and monitoring networks include smart homes equipped with security, identification, and personalization systems; intelligent assembly systems; warehouse inventory control; interactive learning toys; and disaster mitigation. The opportunities emerging from this technology give rise to new definitions of distributed computing and the user interface. Crucial to the success of these ubiquitous networks is the availability of small, lightweight, low-cost network elements, which the authors call PicoNodes. The authors present a configurable architecture that enables these opportunities to be efficiently realized in silicon. They believe that this energy-conscious system design and implementation methodology will lead to radio nodes that are two orders of magnitude more efficient than existing solutions.

Low power design methodologies

Preface. 1. Introduction J.M. Rabaey, et al. Part I: Technology and circuit design levels. 2. Device and technology impact on low power electronics Chenming Hu. 3. Low power circuit technologies C. Svensson, Dake Liu. 4. Energy-recovery CMOS W.C. Athas. 5. Low power clock distribution J.G. Xi, W.W.-M. Dai. Part II: Logic and module design levels. 6. Logic synthesis and module design levels M. Pedram. 7. Low power arithmetic components T.K. Callawy, E.E. Schwartzlander. 8. Low power memory design K. Itoh. Part III: Architecture and system design levels. 9. Low-power microprocessor design S. Gary. 10. Portable video-on-demand in wireless communication T.H. Meng, et al. 11. Algorithm and architectural level methodologies R. Mehra, et al. Index.

Location in distributed ad-hoc wireless sensor networks

Evolving networks of ad-hoc wireless sensing nodes rely heavily on the ability to establish position information. The algorithms presented herein rely on range measurements between pairs of nodes and the a priori coordinates of sparsely located anchor nodes. Clusters of nodes surrounding anchor nodes cooperatively establish confident position estimates through assumptions, checks, and iterative refinements. Once established, these positions are propagated to more distant nodes, allowing the entire network to create an accurate map of itself. Major obstacles include overcoming inaccuracies in range measurements as great as /spl plusmn/50%, as well as the development of initial guesses for node locations in clusters with few or no anchor nodes. Solutions to these problems are presented and discussed, using position error as the primary metric. Algorithms are compared according to position error, scalability, and communication and computational requirements. Early simulations yield average position errors of 5% in the presence of both range and initial position inaccuracies.

Comparison of Methods

There are three methods typically used to convert mechanical motion to an electrical signal. They are: electromagnetic (inductive), electrostatic (capacitive), and piezoelectric. These three methods are all commonly used for inertial sensors as well as for actuators. Conversion of energy intended as a power source rather than a sensor signal will use the same methods, however, the design criteria are significantly different, and therefore the suitability of each method should be re-evaluated in terms of its potential for energy conversion on the meso and micro scale. This chapter will provide an initial, primarily qualitative, comparison of these three methods. The comparison will be used as a basis to identify the areas that merit further detailed analysis.

Optimizing power using transformations

The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area. >

Lightweight time synchronization for sensor networks

This paper presents lightweight tree-based synchronization (LTS) methods for sensor networks. First, a single-hop, pair-wise synchronization scheme is analyzed. This scheme requires the exchange of only three messages and has Gaussian error properties. The single-hop approach is extended to a centralized multi-hop synchronization method. Multi-hop synchronization consists of pair-wise synchronizations performed along the edges of a spanning tree. Multi-hop synchronization requires only n-1 pair-wise synchronizations for a network of n nodes. In addition, we show that the communication complexity and accuracy of multi-hop synchronization is a function of the construction and depth of the spanning tree; several spanning-tree construction algorithms are described. Further, the required refresh rate of multi-hop synchronization is shown as a function of clock drift and the accuracy of single-hop synchronization. Finally, a distributed multi-hop synchronization is presented where nodes keep track of their own clock drift and their synchronization accuracy. In this scheme, nodes initialize their own resynchronization as needed.

Architectural power analysis: The dual bit type method

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSBs), but also for the correlated activity of the most significant bits (MSBs), which contain twos-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%. >

Picoradics for wireless sensor networks: the next challenge in ultra-low-power design

An untapped opportunity in the realm of wireless data lies in low data-rate (<10 kb/s) low-cost wireless transceivers, assembled into distributed networks of sensor and actuator nodes. This enables applications such as smart buildings and highways, environment monitoring, user interfaces, entertainment, factory automation, and robotics While the aggregate system processes large amounts of data, individual nodes participate in a small fraction only (typical data rates <1 kb/s). These ubiquitous networks require that the individual nodes are tiny, easily integratable into the environment, and have negligible cost. The challenges and opportunities in the design of integrated wireless sensor and actuator nodes, to be used in such self-configuring ad-hoc networks, are described. To be viable, the node must be smaller than a couple of mm/sup 3/, cost <